Advanced Micro Devices Corporation

Globalfoundries Inc.

Geoffrey S S Strongin

Dale E Gulick

David W Smith

Qadeer Ahmad Qureshi

Norman M Hack

Norm M Hack

Larry David Hewitt

Brian D McMinn

Alfred C Hartmann

Andrew William Lueck

Wallace Paul Montgomery

In response to entering a secure mode a processor disables access to first predetermined processor information through a sideband interface, while maintaining access to second predetermined processor information through the sideband interface. In the processor, a first interface portion of the sideband interface may provide access to the first predetermined processor information and a second interface portion of the sideband interface may provide access to the second predetermined processor information. The first interface portion is enabled in response to a power-on sequence and is selectably enabled under software control after being disabled on entering the secure mode. The second and additional interface portions may provide access to information related to processor temperature, power management, or machine checks.

Method and apparatus for making a processor sideband interface adhere to secure mode restrictions

A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication of which of the high and low power modes is selected is coupled to the power mode sensitive reordering device as the power mode indication. In the low power mode, memory transactions are reordered to minimize power consumption in memory devices controlled by the memory controller.

Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions

A memory controller generates speculative and non-speculative memory access requests. Several approaches are used to prevent speculative memory access requests from interfering with non-speculative memory access requests. When a request queue is full and contains at least one speculative request, that request is replaced in the memory access request queue with a non-speculative request. A counter associated with a speculative memory access request counts memory access requests. When a predetermined count value is reach, the speculative memory access request is assumed to be stale and retired from the request queue, thereby reducing possible interference by speculative accesses with non-speculative accesses and/or avoiding wasted bandwidth utilization by stale speculative access requests.

Method and apparatus for removing speculative memory accesses from a memory access queue for issuance to memory or discarding

A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of second functions via a communication link that includes a plurality of pipes carrying transactions on the link. Each pipe has a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. Each of the pipes is identified by a pipe identifier that uniquely identifies both the source end and the target end of a respective pipe. Each transaction on the link includes a pipe identification field containing the pipe identifier to associate each of the transactions with one of the pipes. The pipes share the link on a packet multiplexed basis. Each pipe can carry either isochronous or asynchronous transactions.

Computer interconnection bus link layer

A computer system includes a read ahead buffer coupled to a memory controller and an input/output controller coupled to an input/output channel. An I/O device provides an initial read request over the input/output channel which specifies an address in system memory. The memory controller retrieves an amount of data from system memory larger than specified by the read request and provides the requested data to the input/output channel and thus the I/O device. At least a portion of the data retrieved from system memory is stored in the read ahead buffer. The read ahead buffer is marked as valid and identified by at least a portion of the address specified in the read request. When the same I/O device performs a subsequent read access, the I/O request circuit determines whether at least a portion of the address of the subsequent read request matches the portion of the address identifying the read ahead buffer and provides a tag match signal as an indication thereof. Data is then selectively provided from either the read ahead buffer or system memory to the input/output device in response to the second read request according to the tag match signal and the valid indication.

Non-coherent cache buffer for read accesses to system memory

A communication link is provided that carries transactions between functions over multiple logical pipes. An integrated circuit includes a first function and a target concentrator circuit coupled to the first function. The target concentrator has multiple pipes from multiple functions coupled to a single target function. The target concentrator is a circuit that terminates multiple pipes. A receiver circuit, coupled to the communication link, receives transactions carried over the plurality of logical pipes on the communication link. Each pipe is uniquely identified by a pipe identification. The receiver circuit includes a router circuit, that routs transactions having any of the pipe identifications associated with those pipes coupled to the multiple functions, to the target concentrator circuit.

Target side concentrator mechanism for connecting multiple logical pipes to a single function utilizing a computer interconnection bus

A computer system includes a first integrated circuit having a first function and a second integrated circuit having a plurality of second functions. A communication link connects the first integrated circuit and the second integrated circuit. The communication link includes at least one logical pipe having a source side on the first circuit and a target side on the second integrated circuit, the one pipe carrying transactions over the communication link between the first function and the second functions. The pipe is identified by a pipe identification carried in the transactions. A target side distributor circuit is coupled between the second functions and the communication link. The target side distributor circuit receives those transactions from the communication link having the pipe identification. The target side distributor circuit provides transactions received from the communication link having the pipe identification to respective ones of the second functions according to an address field included in the transactions.

Target side distributor mechanism for connecting multiple functions to a single logical pipe of a computer interconnection bus

Read ahead buffer for read accesses to system memory by input/output devices with buffer valid indication

A memory controller detects an approaching end of a currently open page for an access operation for a particular data stream. The memory controller, in response to detecting the approaching end of the currently open page and if the particular data stream is of a predetermined type, such as an isochronous data stream, the memory controller speculatively opens a next page in the memory.

Speculative opening of a new page when approaching page boundary during read/write of isochronous streams

A computer system is described including a CPU core, a memory device storing non-cacheable data, and a bus interface unit (BIU) coupled between the CPU core and the memory device. The CPU core accesses the memory device via the BIU. The BIU includes a stream read buffer, and the system includes logic to determine when to enter a stream read buffer mode. includes a stream read buffer. Following at least one transaction accessing the non-cacheable data within the memory device, the BIU obtains a portion of the non-cacheable data from the memory device, and stores the portion within the stream read buffer. For example, the memory device may include multiple storage locations for storing the non-cacheable data, and the storage locations may have consecutive addresses. Following the least one transaction accessing the non-cacheable data, the BIU may obtain the contents of multiple, consecutively-addressed storage locations of the memory device, and store the contents within the stream read buffer. The stream read buffer may thus be used to store large blocks of non-cacheable data from the memory device. As the CPU core is able to access the stream read buffer faster than the memory device, the efficiencies of data transactions directed to the memory device may be increased. The CPU core may include circuitry for monitoring transactions accessing the non-cacheable data within the memory device.

System and method for entering a stream read buffer mode to store non-cacheable or block data

A system is disclosed for improving the efficiency of data transactions by permitting the length of burst transactions to be modified based upon system performance. A bus interface unit monitors the response times of memory devices, and, if WAIT periods are required before the memory device responds, the bus interface unit increases the length of the burst. Preferably, the bus interface unit includes a table of historical response times of various memory ranges, and determines an optimal burst length for each memory range. When a data transaction is made to a particular memory location, the BIU accesses the table and asserts a BURST signal for a sufficient period of time to accomplish the optimal burst length. After the optimal burst length has been reached in the existing memory transaction, the BURST signal is deasserted to end the burst cycle.

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Austin, TX, United States of America

Geoffrey S S Strongin