Atmel Corporation

Geoffrey S Gongwer

Keith H Gudger

James Fahey

Srinivas Ramamurthy

Neal Berger

Jinglun Eugene Tam

Todd A Randazzo

Bradley J Larsen

Eugene Jinglun Tam

Joe Yu

Steven A Sharp

Wendey E Mueller

James C Khong

William Saiki

William J Saiki

A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions to be loaded into an Instruction Register and then executed. The predefined instructions are designed to follow in sequence after certain other previous instructions. The instructions change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

Boundary scan method for terminating or modifying integrated circuit

Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

Boundary scan system with address dependent instructions

A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.

Configuration control in a programmable logic device using non-volatile

Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state. The use of a flag register allows simplification of the instruction set to register load instructions and basic bulk operation instructions (and a flow through operation using a serial output from the registers), while providing a wide variety of possible block selections for the different bulk operations.

Integrated circuit with flag register for block selection of nonvolatile

A programmable logic device having a plurality of logic cells arranged in groups defining separate logic regions, both regional and multi-regional bus lines, and a crosspoint switch matrix which serves only to route signals from bus lines to inputs of the logic cells without logically combining two or more of the bus signals, i.e. without forming product terms. Rather, all logic is carried out by the logic cells themselves. In particular, the switch matrix is constructed so that each bus line can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell feeds one logic signal back to a regional bus line and can potentially feed back another logic signal through its region's universal select matrix to a universal bus line. The select matrix connects a subset of the region's potential feedback signals to the universal bus.

Programmable logic device with regional and universal signal routing

An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.

Input/output transistors with optimized ESD protection

An EEPROM transistor fabricated with a single polysilicon layer. An MOS transistor is fabricated with a subsurface electrode region defined by a stripe in a first direction. A layer of thin oxide is arranged in a second stripe, perpendicular to the first stripe and a polysilicon layer, arranged in a third stripe is disposed over the second stripe of thin oxide. An adjoining parallel plate capacitor is formed by a subsurface region of the same conductivity type as the subsurface electrodes in the first stripe. An insulative second plate of thin oxide is joined to the second stripe and a third plate of the capacitor is formed by a polysilicon plate over the oxide plate. Vertical metallization stripes in the first direction may contact with some components, while parallel metal stripes in a second layer in a perpendicular direction may contact with the remaining members. The stripe geometry allows lateral and vertical four-way symmetry for implementation of a large number of memory storage cells on a chip or wafer.

Single layer polysilicon EEPROM having uniform thickness gate

A voltage limiting device having gate and drain electrodes that include a serpentine configuration to form a pattern of breakdown corners at the traversals of the gate electrode over the drain electrode. The serpentine configuration may define a plurality of fingers. The number of breakdown corners determines the current-voltage (I-V) characteristics of the voltage limiting device. Either one of the gate electrode or the drain electrode may be configured in a manner to provide repeated traversals of one electrode over the other.

Voltage limiting device having improved gate-aided breakdown

An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers in two different macrocells, and at least one contact connects in this manner to separate logic regions of the logic circuit. The flip-flop register in the macrocell has a choice of data inputs selected by another multiplexer from among at least one logic signal from the logic circuit and at least one signal applied to an external contact.

Integrated logic circuit with functionally flexible input/output

A programmable logic device having multiple first logic arrays, such as AND arrays, each with a different set of inputs and all simultaneously operating, in which the outputs from two or more first logic arrays are shared in a single speed logic gate or array, such as an OR gate or array. In one embodiment, there are N first logic arrays and M second logic arrays connected such that each second logic array receives intermediate terms from every first logic array and intermediate terms from each first logic array are shared by plural second logic arrays. In a second embodiment, there are N first logic arrays and a plurality of second logic gates connected so that at least some of the second logic gates receive intermediate terms from two adjacent first logic arrays.

Programmable logic device with multiple shared logic arrays

A clock circuit having a logic gate with an output supplying a clock signal to a clock input of a storage element and with plural inputs, including an input connected to an external contact for receiving an external clock signal and an input connected to a logic circuit to receive a logic term, such as a product term or sum-of-products term. The logic gate logically combines the internally generated logic with the external clock signal to produce the clock signal for the storage element. The logic gate may be an AND, OR, NAND or NOR gate. A multiplexer with an output connected to an input of the logic gate and responsive to a control signal may select one of two or more logic terms, one of two or more external clock signals, or a fixed voltage signal.

Clock selection for storage elements of integrated circuits

A programmable logic device having a programmable AND (product term) array formed with input terms on both global and local busses and with both global and local product term lines. Each macrocell of the device, whether as input/output macrocell connected to an I/O pin or a buried macrocell providing only feedback, connects to and receives an inputs both global and local product terms. In one embodiment, global product terms are connectable to the global bus and to a local bus corresponding to a particular group or quadrant of macrocells. Local product terms are only connectable to that local bus, and thus only a fraction of the terms available to the global product terms. In an alternate embodiment, global product terms are connectable to the global bus and to a set of local busses which is a prope subset of all of the local busses. Local product terms are connectable only to the particular local bus assigned to a particular group or quadrant of macrocells and to a fraction of the terms on the global bus.

Programmable logic device with global and local product terms

A logic output control circuit for selecting between stored and nonstored outputs from a data input and a clock having a data pass gate MOS transistor receiving a logic signal at its data input and either blocking the signal or passing it to a cross-coupled inverter gate latch depending on a control signal at its control gate terminal. The control signal is derived in one embodiment by a logic gate with a programming signal input, a clock input and a control signal output, and in a second embodiment by a set of pass gate transistors respectively receiving a clock signal and a fixed level signal and controlled by a programming signal. When the programming signal has one logic level, the data pass transistor is always on and the logic signal flows continually to the output. When the programming signal has the other logic level, the data pass transistor switches on and off with the clock signal and the circuit operates as a latch. The clock signal may be an input clock or a pulsed clock which is an edge triggered version of the pin clock signal.

Logic output control circuit for a latch

A logic array device having an input switch detector circuit for each input signal line leading into an array of logic gates and means for enabling the array whenever and only when a change in logic level of at least one input signal is detected. An AND array has a pull-up element connected to the device's power supply, which element is turned on by an AND array enable signal generated by a circuit responsive to switch detection. Likewise, OR gates or NOR gate/invertor combinations have a pull-down or pull-up element which is turned on by an OR array enable signal. The AND array is enabled first, followed by the OR gate or gates. The OR gate or gates is disabled first before the AND gate is disabled. Disablement of the gates when no input level switch is occurring reduces power consumption without affecting device speed, while the order of enablement and disablement prevents glitches or loss of the output signal level during enablement and disablement.

Growing community of inventors

Campbell, CA, United States of America

Geoffrey S Gongwer