Tandem Computers Incorporated

Hewlett-packard Development Company, L.p.

Geoffrey I Iswandhi

David J Garcia

William J Watson

David P Sonnier

Robert W Horst

William P Bunton

William Edward Baker

Daniel L Fowler

Mihai Damian

Frank A Williams

Paul N Hintikka

John D Coddington

John C Krause

William F Bruckert

Richard W Cutts, Jr

Susan S Meredith

Linda Ellen Zalzala

Gary F Campbell

Vijaykumar Immanuel

John Michael Brown

Douglas E Jewett

Steven C Meyers

Yie-Fong Dan

Stephen G Low

Kenneth K Chan

Patricia L Whiteside

Martin W Sanner

Randall G Banton

Wing M Chan

James Stevens Klecka

James E Korpi

Wendy B Bartlett

Jay A Zwagerman

Curtis Willard Jones, Jr

Duc Manh Hoang

David Joseph Kinkade

Vijay Immanuel

Stephen H Miller

Barry Lee Drexler

Harry Frank Elrod

Steven G Silverman

Zubair Hussain

David L Bernick

James E Smith

Encryption key rotation is performed in computing environments having mirrored volumes by initializing a target storage media with a new key, performing a mirror revive operation from a first storage media to the target storage media, and configuring the first storage media and the target storage media to comprise a mirrored volume.

Key rotation for encrypted storage media using a mirrored volume revive operation

An I/O module is provided to service I/O requests from a host to access storage media. Data blocks of the storage media are encrypted with an old key, and the I/O module performs key rotation to cause data blocks to be re-encrypted with a new key.

Key rotation for encrypted storage media

Storage media is coupled to first and second storage controllers. When the first storage controller performs encryption key rotation, the first storage controller writes a key rotation message to a storage controller metadata section of the storage media indicating that key rotation is underway. The second storage controller observes the key rotation message indicating that key rotation is underway and suspends access by the second storage controller to encrypted portions of the storage media.

Encryption key rotation messages written and observed by storage controllers via storage media

A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Storage access validation to data messages using partial storage address

A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.

Network message routing using routing table information and supplemental

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.

Interrupt message delivery identified by storage location of received

A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.

Method for verifying responses to messages using a barrier message

In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

Input/output system for multiprocessors

Growing community of inventors

Sunnyvale, CA, United States of America

Geoffrey I Iswandhi