Koninklijke Philips Corporation N.v.

Nxp B.v.

Agere Systems Inc.

Geoffrey Francis Burns

Krishnamurthy Vaidyanathan

Karl R Wittig

Olivier Gay-Bellile

Xavier Marchal

Karl Raymond Wittig

A backward compatible enhancement to ATSC-VSB transmissions is provided to enable intra-field channel estimation for better channel equalization. One or more time-frequency waveforms are inserted into the transmitted signal with systematic time and frequency variation synchronized to the currently available field sync. A coherent demodulator may then directly estimate the channel frequency response. The power of the inserted waveform(s) is small compared to the existing 8-VSB signal, such that existing receivers will function as intended with only minimal degradation of performance.

Method to improve ATSC-VSB transceiver performance employing a time-frequency waveform processor

A method and apparatus for efficiently generating complex sinusoids of a desired frequency by multiplying a phasor by a predetermined value once every sampling interval, and using the highest order bits within the phasor to identify if the phasor is at an integer multiple 45 degrees and substituting components in the phasor if it is determined that the phasor is an integer multiple of 45 degrees. If the phasor is not identified as being an integer multiple of 45 degrees then an error factor for both the real and imaginary components is determined and the real and imaginary components are corrected by removing the error factor.

Free-running numerically-controlled oscillator using complex multiplication with compensation for amplitude variation due to cumulative round-off errors

A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus and each performing a different function of the first processing. The first domain processors include a first domain control processor for controlling the first processing of the first domain. The multi-processor unit also includes a second domain for second processing of the first processed data depending on a second domain configuration and having multiple second domain processors each connected to the communication apparatus and each performing a different function of the second processing. The second domain processors include a second domain control processor for controlling the second processing of the second domain. The multi-processor unit also including a global control processor connected to the communication means for providing the first domain configuration information and the second domain configuration information through the communication means for configuring the first and second domains.

Control architecture for a high-throughput multi-processor channel decoding system

A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the 'delay limit' value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo 'delay-limit', when the processing loop starts a new iteration.

Programmable delay indexed data path register file for array processing

The invention relates to a multi-standard digital receiver, in a digital video transmission system. It comprises a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising:

Multi-standard channel decoder

A multi-standard channel decoder for real-time digital broadcast reception has a plurality of processors connected to a sample-based communication unit for sample-based processing and connected to a block-based communication unit for block-based processing. The channel decoder is able to use the same processors to channel decode sample-based transmissions such as 8-VSB broadcasts and block-based transmissions such as COFDM broadcasts.

Multi-standard channel decoder for real-time digital broadcast reception

An apparatus and method of a shared correlator system for a code division, multiple access (CDMA) receiver employs scheduling of correlation operations with identification tags (ID-tags). The scheduling allows for shared vector generation and correlation operations between processing units by pipeline processing. The shared correlator schedules correlation operations requested by processing units, generates matched-filter PN vectors associated with the identification tags for the correlation operations, and provides correlation results for the correlation operations. Scheduling may be implemented with a control processor, scheduler and memory. The control processor determines the matched-filter PN vector information for a requested operation using the current state of a reference PN code sequence, and this information is stored as the ID-tag. The control processor stores the ID-tag at an address in memory associated with a slot of a periodic symbol schedule. A counter of the scheduler steps through each memory address to provide an ID-tag for each slot. The ID-tag allows the matched-filter PN vector information for a requested correlation operation to be provided to the vector generator and vector correlator to generate the matched-filter PN vector for the slot.

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Ridgefield, CT, United States of America

Geoffrey Francis Burns