Advanced Micro Devices Corporation

Other

Motorola Corporation

Legerity, Inc.

Advanced Miere Devices, Inc.

Geoffrey E Brehmer

Joe W Peterson

Carlin D Cabler

Dale E Gulick

Larry David Hewitt

Paul G Schnizlein

Alfredo R Linz

David N Suggs

Glen W Brown

David E Norris

Michael E Spak

Jeffrey M Blumenthal

Ryan E Feemster

Martin P Soques

Michael Hogan

David J Guercio

Alan T Torok

Daren L Allee

Harry S Jackson

James R Carbery

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

An intermediate frequency gain and rectifying stage for an IF system is implemented with a high swing folded-casecode structure terminated into a current-mirror load. The signal-path outputs are derived from the current-mirror loads, and the rectification and current-limiting RSSI functions are performed with two additional constant-current sources and two additional current-mirror loads. One load current from one leg or current path of the signal-path gain-stage is mirrored into a constant-current source and a second current-mirror structure. A second leg or current path of the signal-path gain-stage is likewise mirrored into yet another constant-current source and another current-mirror structure. When the input signal is not present, the load currents in the signal-path gain-stage are equal and the rectified output signal on an output node IOUT is constant or set to zero. With a differential input signal present, the load currents in the signal-path gain-stage produce a plus delta-current and minus delta-current. The plus delta-current, which represents a difference between the current in one of the legs of the signal-path gain-stage and the current of a corresponding constant current source, is mirrored to generate the RSSI current output signal at the IOUT node. Likewise, during the negative-half input-cycle the signal-path load currents are again mirrored and only the plus delta-load-current is rectified and output on the output node IOUT.

Intermediate frequency gain stage with rectifier

An IF receiver system includes an IF signal path formed by an IF amplifier section, a bandpass filter, and a limiter section. An RSSI (Receive Signal Strength Indicator) circuit is coupled to the IF amplifier section and the limiter section and generates an RSSI output signal which varies linearly with logrithmic changes in input power. A storage unit is coupled to the RSSI circuit and is configured to store a value which controls current limiting associated with the RSSI circuit. In one specific implementation, the limiter section includes a plurality of serially coupled limiter stages. The RSSI circuit includes a plurality of rectifying stages, wherein a separate rectifying stage is coupled to an input of a corresponding limiter stage. An additional rectifying stage is coupled to an output of a last of the limiting stages. The value within the storage unit controls the extent of current limiting associated with the additional rectifying stage.

Programmable intermediate frequency RSSI system including an adjustable

A fully differential operational amplifier with improved common mode circuitry for low supply voltage applications is disclosed. The amplifier includes inventing and non-inventing inputs and dual-ended invented and non-invented outputs. The amplifier also includes source transistors for pulling the output to obtain particular output voltage swing. Connections between the inputs and outputs include DC biasing circuitry. The amplifier includes a transistor of select size and characteristics to compensate for voltage drop due to other transistors of the amplifier. Common mode circuitry of the amplifier provides a high level of common mode reconstruction.

Low voltage fully differential operational amplifier with improved

A phase-locked-loop circuit including a prescaler which divides the frequency of an output signal to thereby generate a frequency-divided signal which is provided as a feedback signal to a phase detector of the phase-locked-loop circuit. The prescaler includes a plurality of analog flip-flop circuits serially connected in a chain, with one or more outputs of latter analog flip-flop stages in the chain being fed back to one or more inputs of the first analog flip-flop. Embedded logic is integrated with the differential input pair of the first analog flip-flop to conditionally control the output of the first analog flip-flop based upon the feedback signals from the latter flip-flop stages. The analog flip-flop with embedded logic includes a master section for setting a state of a differential set up signal in response to an occurrence of a first phase of a clock signal. The master section includes a differential pair of transistors coupled to differentially control a flow current through a first and a second load during a second phase of the clock signal. First and second logic circuits are provided in the place of an input differential pair of transistors which control the flow of current through the first and second loads during the first phase of the clock signal. The first logic circuit includes a first transistor and a second transistor each connected to conduct current which flows through the first load. A second logic circuit may be similarly configured with third and fourth transistors which conduct a current which flows through the second load.

High speed analog flip-flop with embedded logic and phase-locked-loop

An operational amplifier circuit is provided which includes: 1) a first folded-cascode gain stage having a differential pair of natural V.sub.T devices which are P-channel transistors; 2) a second gain stage connected to an output of the first folded-cascode gain stage; 3) a slave source follower stage connected to an output of the second gain stage; 4) a second folded-cascode stage connected to an output of the slave source follower stage; and 5) a source follower output stage connected to an output of the second folded-cascode gain stage. The high swing output stage of the operational amplifier, which includes stages 3-5 above, includes a pair of natural V.sub.T devices which are P-channel transistors.

High swing low power general purpose operational amplifier

A high swing, low power output stage for an operational amplifier is provided which includes: 1) a folded-cascode gain stage having a differential pair of natural V.sub.T devices, which are preferably P-channel transistors; 2) a source-follower input stage connected to the folded-cascode gain stage and to the input of the high swing output stage; and 3) a source-follower output stage connected to the folded-cascode gain stage connected to an output of the source-follower stage and to the output of the high swing output stage. The high swing output stage also includes a compensation capacitor which is used to provide dominant pole frequency compensation for the high swing output stage.

High swing, low power output stage for an operational amplifier

A strobed comparator for a large common mode range is described, which includes a mixture of natural and enhancement transistors, and a high-swing folded-cascode architecture, to achieve an improved dynamic range suitable for audio applications.

Strobed comparator for a large common mode range

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

An operational amplifier for low supply voltage applications. The operational amplifier includes inverting and non-inverting inputs and a single-ended output. The operational amplifier also includes source transistors for pushing the output and sink transistors for pulling the output to obtain particular output voltage swing. Connections between the inputs and output include DC biasing circuitry. In low supply voltage applications, voltage drop due to transistors of amplifier circuitry can be significant and can affect possible range of output voltage swing. The DC biasing circuitry includes four identically sized n-channel transistors; three of the n-channel transistors receive a second bias current input and one of the n-channel transistors receives a first bias current input, identical to the first three identically sized n-channel cascode transistors are connected to the n-channel transistor that receives the first bias current input and to two of the n-channel transistors receiving the second bias current input; the other n-channel transistor receives the second bias current input and is connected to a correcting transistor of select size and characteristics. The correcting transistor serves to maintain mirrored currents between each of the source transistors and each of the sink transistors to eliminate the implications of inequivalent voltage drop across corresponding series of transistors in the amplifier so that the range of output voltage swing, even in low supply voltage applications, closely approaches the value of the power supply voltage.

Operational amplifier for low supply voltage applications

An improved comparator circuit is provided for comparing two input signals and producing a resulting digital output. The comparator circuit uses a single cascode devices and current mirror circuit parallel coupled to two differential amplifier stages. One differential amplifier stage receives differential input signals and the other differential amplifier stage receives a variable reference voltage and a feedback voltage from the output of the comparator. The reference voltage is varied according to user requirements. The reference voltage can be varied to any voltage within the range of the input signals placed on the differential amplifier stage. Hysteresis differential voltage on the input differential amplifier stage can be accurately controlled by varying the biasing current and reference voltage placed on the hysteresis differential amplifier stage.

Voltage comparator with hysteresis

An op-amp comprising a single gain stage amplifier cascaded with a buffer and an output stage. The buffer comprises an amplifier which isolates the gain stage from the output stage to prevent loading of the gain stage and create a more linear op-amp. For frequency compensation, the op-amp utilizes MOSFETs connected in a reversed biased configuration as load compensation capacitors. This technique reduces the non-linear effects of MOSFET gate capacitors utilized in conventional Miller compensation schemes and allows for digital fabrication technology of low distortion, low power supply operational amplifier design.

Low distortion operational amplifier

A voltage limiter (20) includes a resistor (21) receiving an input signal on a first terminal and providing an output signal on a second terminal, and a capacitor (22) connected between the second terminal of the resistor (21) and ground. Two transistors (23,26) biased by first and second bias voltages, respectively, are connected between the second terminal of the resistor and a second voltage terminal to clamp the output voltage between high and low voltage limits. A single-ended to differential converter (60) uses two such voltage limiters. A first voltage limiter (90) receives an input voltage, and has an output terminal connected to a positive input terminal of an amplifier (100). A second voltage limiter (92) has an input terminal connected to the second voltage terminal and an output terminal connected to a negative input terminal of the amplifier (100). A shared capacitor (83) is coupled between second terminals of resistors of the first (90) and second (92) voltage limiters.

Voltage limiter and single-ended to differential converter using same

A fully differential non-linear amplifier includes an operational amplifier (12), a first input resistor (R1), a second input resistor (R2), a first feedback resistor (R3), a second feedback resistor (R4), a first clamping network (CN1), and a second clamping network (CN2). The first clamping network (CN1) is formed of a first P-channel clamping transistor (P10) and a first N-channel clamping transistor (N10). The second clamping network (CN2) is formed of a second P-channel clamping transistor (P12) and a second N-channel clamping transistor (N12). The gates of the first and second P-channel clamping transistors (P10, P12) are connected to receive a P-bias signal. The gates of the first and second N-channel clamping transistors (N10, N12) are connected to receive a N-bias signal. The non-linear amplifier clamps its differential output signal to a constant voltage level independent of variations in process and temperature.

Fully differential non-linear amplifier

A transmitter for converting a binary digital signal into a pseudo-ternary signal. The transmitter has been designed so as to overcome the problem of line clamping during a power-down condition, provides a current limiting function, and reduces the ringing problem associated with driving an inductive load with a high impedance source.

Growing community of inventors

Lexington, TX, United States of America

Geoffrey E Brehmer