Alcatel

Geoffrey Dive

Michael Joachim Wolf

Werner Beisel

J&uuml;rgen Kasper

The present invention relates to a method for the synchronization of a first and a least one second module, each having a clock generator. The invention furthermore relates to such modules, a master program module, a slave program module and a device for this purpose. It is proposed that the first module, transmits a first clock signal generated by its clock generator to the second module, which synchronizes its clock generator with the first clock signal. The second module transmits a second clock signal generated by its clock generator that is synchronized with the first clock signal to the first module, which determines a time difference value between the first clock signal and the second clock signal, which time difference value is essentially due the transmission time of the first and the second clock signal between the first and the second module. The first module transmits an item of information about the (first) time difference value to the second module, which adjusts its clock generator on the basis of said information.

Two-step synchronization method in which two modules are synchronized first by frequency followed by a synchronization in phase

A synchronous transmission system is disclosed in which the transmission paths (leased lines) extend over several individual transmission systems (Sx). Monitoring devices (NIM) with access to at least one byte of the control data area are provided in synchronous transmission systems to write data into or read data out of the control data area. The monitoring devices (NIM) may thus be controlled and monitored by a signal source (S ).

Synchronous transmission system with fault location function and monitoring device therefor

A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

Synchronization device for a synchronous digital message transmission system and process for producing a synchronous output signal

A transmission system is indicated for digital signals combined into a multiplex signal, and a network element for such a transmission system. Each network element contains an adapter circuit to balance phase variations in an incoming multiplex signal. The adapter circuit has a buffer memory (,) for payload data bytes, a write address generator (,) which controls the buffer memory (,) in a way so that a number of payload data bytes is stored within one write cycle, and has a read address generator (,) which controls the buffer memory (,) in a way so that the number of payload data bytes stored within the write cycle is greater than the number of payload data bytes read during the read cycle. Each network element has a sort facility (,) which sorts the read payload data bytes, so that a multiplex signal that is transmitted by a network element has the established frame format.

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Aspach, Germany

Geoffrey Dive