Nortel Networks Corporation

Bay Networks, Inc.

Other

Geoffrey B Ladwig

Richard L Angle

Edward S Harriman

Nanying Yin

Shantigram V Jagannath

Jeffrey V Bean

William Melaragni

Marvin Scheinbart

John J Fitzgerald

A method and apparatus are provided for scheduling unicast and multicast data in an input-queued network device. According to one aspect of the present invention, a combined schedule is created by pipelined staging of multicast and unicast scheduling. Multicast cells are scheduled for transmission among multiple interfaces of a crossbar by performing a multicast cell scheduling cycle for multiple classes of service that are supported by the network device. Then, unicast cells are scheduled for transmission among the interfaces at a lower priority than the previously scheduled multicast cells by performing a unicast cell scheduling cycle for the multiple classes of service using only those interfaces that remain unmatched after completion of the multicast cell scheduling cycle.

Multicast and unicast scheduling for a network device

A method and apparatus are provided for scheduling multicast data in an input-queued network device. A fabric arbiter receives a transmit request associated with multiple input ports. The transmit request identifies those of the output ports to which pending multicast cells are ready to be transmitted, if any. The fabric arbiter receives a backpressure signal from a backpressuring output port. Then, based upon the backpressure signal the fabric arbiter schedules multicast cells for transmission across the fabric. If the size of a multicast queue exceeds a predetermined threshold, then the fabric arbiter ignores the backpressure signal and causes the head-of-line multicast cell from the multicast queue to be transferred to the backpressuring output port. Otherwise, the fabric arbiter prevents multicast cells from being transferred to the backpressuring output port by masking requests destined for the backpressuring output port thereby removing the backpressuring output port from consideration during multicast scheduling.

Backpressure mechanism for a network device

A method and apparatus are provided for scheduling multicast data in an input-queued network device. According to one aspect of the present invention, deterministic and bounded delay for high priority multicast cells is guaranteed by the multicast scheduler. The scheduler receives a transmit request associated with each of a plurality of input ports. The transmit request identifies output ports to which pending multicast cells are ready to be transmitted, if any. Then, for each of multiple classes of service, the scheduler performs a single scheduling iteration. The single scheduling iteration includes a grant phase, an accept phase, and an update phase. During the grant phase, the scheduler grants one or more of the input ports access to the fabric by issuing grants based upon the transmit requests and a priority indicator that identifies an input port that is given scheduling priority for the scheduling iteration. During the accept phase, on behalf of each of the input ports, the scheduler accepts all grants corresponding to the input port. Finally, during the update phase, the scheduler updates the priority indicator for use in a subsequent scheduling cycle.

Multicast scheduling for a network device

An apparatus and method for storage of memory packets with a high aggregate bandwidth is disclosed. An odd-even memory bank structure effectively doubles the memory available for packet storage. A packet memory arbitration scheme aligns access of devices reading and writing into packet memory allowing full-rate access to the packet memory.

Apparatus and method for interleaved packet storage

A method and apparatus are provided for scheduling unicast and multicast data in an input-queued network device. According to one aspect of the present invention, multicast scheduling is triggered by a programmable parameter. Each scheduling timeslot of a set of possible scheduling timeslots, unicast cell scheduling is performed. Multicast cell scheduling is performed in parallel with and independent of the unicast cell scheduling during scheduling timeslots in which a programmable multicast scheduling frequency parameter satisfies a predetermined condition.

Programmable multicast scheduling for a network device

A memory management technique for maintaining packet order in a packet processing system involves maintaining a START indicator and a VALID indicator for each memory block in a packet memory. Packets are written in a number of successive memory blocks, and the START indicator corresponding to the first memory block of the number of successive memory blocks is set to indicate that the packet is available for processing. The packets are processed by a packet processor. When the packet processor completes the processing of a particular packet, the VALID indicator corresponding to the first memory block associated with that packet is set to indicate that the packet is ready to be forwarded. The packet may become ready to be forwarded out of order. However, the packets are forwarded in first-in-first-out order by processing the packets in first-in-first-out order and only forwarding a particular packet if the VALID indicator corresponding to the first memory block associated with that packet is set to indicate that the packet is ready to be forwarded. Thus, a packet is not forwarded unless and until all previous packets have been forwarded, even if the packet is ready to be forwarded before one or more previous packets.

Memory management technique for maintaining packet order in a packet processing system

A method and apparatus are provided for scheduling multicast data in an input-queued network device. According to one aspect of the present invention, the head-of-line blocking problem is avoided for multicast queues. A fabric arbiter receives a transmit request associated with multiple input ports. The transmit request identifies those of the output ports to which pending multicast cells are ready to be transmitted, if any. The fabric arbiter receives a backpressure signal from a backpressuring output port. Then, based upon the backpressure signal the fabric arbiter schedules multicast cells for transmission across the fabric. If the size of a multicast queue exceeds a predetermined threshold, then the fabric arbiter ignores the backpressure signal and causes the head-of-line multicast cell from the multicast queue to be transferred to the backpressuring output port. Otherwise, the fabric arbiter prevents multicast cells from being transferred to the backpressuring output port by masking requests destined for the backpressuring output port thereby removing the backpressuring output port from consideration during multicast scheduling.

The present invention is a method and apparatus for interconnection system. A first front connector is located at a side of a first front card to provide first contacts for first signal traces on the first front card. A second front connector located at a side of a second front card to provide second contacts for second signal traces on the second front card. A mating connector has first and second receptacles and is located alongside of a rear card. The mating connector electrically connects the first contacts of the first signal traces to the second contacts of the second signal traces via contacts in the first and second receptacles. The first and second receptacles couple to the first and second front connectors, respectively. The rear card is positioned in a substantially orthogonal direction to the first and second front cards.

High throughput interconnection system using orthogonal connectors

A method for handling cache misses in a computer system. A prefetch unit fetches an instruction for execution by one of a plurality of coprocessors. When the preferred embodiment of the present invention experiences a cache miss in a prefetch unit, the process for which an instruction is being fetched is passed off to a memory processor which executes a read of the missing cache line in memory. While the process is executing in memory processor, or queued by the scheduler for execution of the same instruction, the prefetch unit continues to dispatch other processes from the its queue to the other processors. Thus, the computer system, including the processors, do not stall. Processors continue to execute processes. The prefetch unit continues to dispatch processes. When the memory read is completed, the process in which the cache miss occurred is rescheduled by the scheduler. The prefetch again attempts to fetch and decode the instruction and arguments. If another cache miss occurs, the process is again dispatched to the memory processor. Upon reading the cache line, the memory processor again sends the process to the scheduler's queue.

Method and apparatus for handling cache misses in a computer system

A method and apparatus for maintaining an order of processing data packets. One embodiment of the invention includes a first stage of data packet processing, which sequentially receives a plurality of independent data packets. The data packet are to be processed at the first stage in parallel. The plurality of independent data packets are then permitted to continue processing at a separate stage only in the order the independent data packets were received at the first stage of the data packet processing. In one embodiment, the invention includes assigning a sequence number to a first independent data packet of the plurality of packets prior to the first stage of data packet processing. Thereafter, the invention includes comparing the sequence number assigned to the first independent data packet to a servicing number. In response to the sequence number and the servicing number being different by N, wherein N is an integer, the invention permits the first independent packet to continue processing at a separate stage. Thereafter, the servicing number is incremented by replacing the servicing number with the sequence number.

Method and apparatus for maintaining an order of data packets

A computer system architecture in which each processor has its own memory, strategically distributed along the stages of an execution pipeline of the processor, to provide fast access to often used information, such as the contents of the address and data registers, the program counter, etc. Memory storage is strategically located in close physical proximity to a stage in an execution pipeline at which memory is commonly or repeatedly accessed. Coupled to the pipeline at various stages are small memory cells for storing information that is consistently and repeatedly requested at that stage in the execution pipeline. The speed of the execution pipeline in a processor is critical to overall performance of the processor and the computer architecture of the present invention as a whole. To that end, the clock cycle time at which the pipeline is operated is increased as much as the operating characteristics of the logic and associated circuitry will allow. Generally, access times for memory are slower than the clock cycle times at which the pipeline logic can operate. Thus, there is a point of diminishing return at which increasing the clock cycle time of the pipeline is less advantageous if the pipeline must wait for memory access to complete. Thus, there is provided two sets of strategically located memory cells distributed along the execution pipeline of a processor, and alternately accesses the memory cells.

Distributed pipeline memory architecture for a computer system with even and odd pids

A method for searching for keys of arbitrary width in a table in a memory of a computer system by repeatedly executing lookup instructions on a lookup processor. The lookup processor executes a lookup instruction to find a key in a table. The execution of the lookup instruction results in a key being found, or a key not being found. If the key is not found, the process is requeued by a scheduler with the program counter register for the process pointing to the instruction immediately following the lookup instruction, i.e., the next instruction. In the event the key is found in the table, the entry in the table associated with the key contains the memory address of the next instruction to be executed. This memory address is loaded into the program counter register associated with the process in which the lookup instruction was executed. The scheduler requeues the process, later dequeues it, and the instruction pointed to by the program counter register is fetched by an instruction fetch unit. A dispatcher sends the process to the appropriate processor for execution of the next instruction. In this way, a branch to any instruction in the process can be performed. The instruction pointed to by the PC register can be another lookup instruction in the process. In this way, multiple lookup instructions can be sequentially executed, each specifying a different portion of a key of arbitrary width, or each specifying a particular key in a sequence of keys being searched for.

Method for branching to an instruction in a computer program at a memory

In a search method for a radix search tree, a logic circuit for computing the actual offset of an entry in a node in a tree. The logic circuit accepts a pointer to a node in the tree, along with an associated bit mask indicating which entries are present in the node. The logic circuit further receives an entry value, the offset of which from the beginning of the node is to be computed by the logic circuit. The logic circuit utilizes Boolean AND gates to mask off higher order bits in the bit mask above the bit position corresponding to the entry value received by the logic circuit. The lower order bits in the bit mask, up to but not including the bit position corresponding to the entry value, are added together to determine the number of entries that exist at a lower offset in the node than the entry indicated by the entry value. The logic circuit combines the pointer received with the sum computed to calculate the offset memory address at which the entry is located in the node.

Radix tree search logic

A computer implemented method for searching for a key in a radix search tree in a memory of a computer system. A table of keys is organized in a radix search tree stored in a memory of a computer system. The keys are divided into a string of symbols. Each node in the tree corresponds to a symbol. A path from a root node to a leaf node at level n in the tree represents a string of n symbols comprising a key. Each node is capable of having m possible entries corresponding to m possible symbol values. Each entry comprises a pointer to a son node and an existence map indicating which entries exist in the son node. In the preferred embodiment, the existence map is a bit mask that indicates, based on bit positions enabled and disabled in the bit mask, which entries exist in the son node pointed to by the pointer. By providing an existence map along with the pointer to a son node, m memory locations for m entries are allocated for the son node only if all of the m possible entries are used. Memory locations for entries that would otherwise be empty are not allocated, thereby minimizing memory resources required by a radix search tree.

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Chelmsford, MA, United States of America

Geoffrey B Ladwig