Motorola Corporation

Freescale Semiconductor,inc.

Geoffrey B Hall

James W Miller

Susan H Downey

Fujio Takeda

Joseph Y Chan

Michael A Stockinger

Marc Laurent Tarabbia

Dzung T Tran

Michael G Khazhinsky

Kelvin E McCollough

Pedro Ovalle

Jose A Camarena

Matthew D Akers

Alexander Alekseevich Krasin

Jeffrey R Hardesty

Vishnu G Kamat

Michael Priel

An integrated circuit () has a wire bond pad (). The wire bond pad () is formed on a passivation layer () over active circuitry () and/or electrical interconnect layers () of the integrated circuit (). The wire bond pad () is connected to a plurality of final metal layer portions (). The plurality of final metal layer portions () are formed in a final interconnect layer of the interconnect layers (). In one embodiment, the bond pad () is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad () allows routing of conductors in a final metal layer () directly underlying the bond pad (), thus allowing the surface area of the semiconductor die to be reduced.

Semiconductor device having a wire bond pad and method therefor

An Electrostatic Discharge (ESD) protection circuit ( ) includes a plurality of I/O and power supply pad cells ( ) that comprise external pads ( ) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices ( ) coupled in parallel between an ESD bus ( ) and a VSS bus ( ) and distributed among the plurality of pad cells. One or more trigger circuits ( ) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus ( ) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.

Electrostatic discharge protection circuitry and method of operation

An integrated circuit ( ) has a wire bond pad ( ). The wire bond pad ( ) is formed on a passivation layer ( ) over active circuitry ( ) and/or electrical interconnect layers ( ) of the integrated circuit ( ). The wire bond pad ( ) is connected to a plurality of final metal layer portions ( ). The plurality of final metal layer portions ( ) are formed in a final interconnect layer of the interconnect layers ( ). In one embodiment, the bond pad ( ) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad ( ) allows routing of conductors in a final metal layer ( ) directly underlying the bond pad ( ), thus allowing the surface area of the semiconductor die to be reduced.

An output buffer ( ) has a pre-driver circuit ( ) for controlling a voltage transition of an output signal from an output driver transistor ( ). The pre-driver circuit ( ) provides an input that slightly leads the gate voltage of the output driver transistor ( ). The pre-driver circuit ( ) includes a configurable resistance circuit ( ) that provides one resistance value at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector ( ) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.

Output buffer having a pre-driver transition controller

A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate. A third capacitor has a p-type polysilicon top plate coupled to the first terminal, an accumulation/depletion region bottom plate coupled to the second terminal, and a third dielectric region between its top and bottom plates. The fourth capacitor has a p-type polysilicon terminal coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plates.

Linear capacitor structure in a CMOS process

A circuit (,) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (,) includes cascoded NMOSFETs (,), with the upper NMOSFET (,) connected to voltage divider circuitry (,). The voltage divider circuitry (,) provides a first bias voltage to the gate of the upper NMOSFET (,) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately,of the drain voltage of the upper NMOSFET (,). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.

Electrostatic discharge circuit

A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.

Load capacitance compensated buffer, apparatus and method thereof

A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

Growing community of inventors

Austin, TX, United States of America

Geoffrey B Hall