Fujitsu Corporation

Gensuke Goto

Hajime Kubosawa

Shinji Sato

A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal arid is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.

Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability

A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal and is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.

An adder circuit includes a 4-2 compression circuit in which a NAND signal of a first input signal and a second input signal and an exclusive-OR signal of the first and second signals are produced. When the exclusive-OR output is true, a third signal is output as an intermediate carry-out signal while when the exclusive-OR signal is false, a NOT signal of the NAND signal is output as the intermediate carry-out signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.

Compression circuit of an adder circuit

A plurality of multiplicand bit transmission lines and a plurality of multiplier bit transmission lines or their decoding signal transmission lines are arranged in a two-dimensional plane, and partial product generators are arranged at their intersections. A plurality of rows of first multi-input adders are arranged at predetermined numbers of rows, and at least one row of second multi-input adders are arranged at predetermined numbers of the first multi-input adders. A basic cell is formed by a predetermined number of partial product generators and one first multi-input adder, and the basic cells are repetitively arranged to obtain a rectangular configuration.

High speed digital parallel multiplier

A binary operator comprises a plurality of carry select adder circuits each including a cumulative carry propagate signal generating means and a cumulative carry generate signal generating means and/or a plurality of block look ahead carry generator circuits each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means and a real carry signal generating means. The carry select adder circuit does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on a carry propagate signal, a cumulative carry propagate signal and a cumulative carry generate signal which are necessary for generating the presumed sum signal pair and a real carry signal to calculate the real sum signal. The block look ahead carry generator circuit does not simultaneously generate two presumed carry signals and select and output one of the presumed carry signals, but uses a cumulative block carry propagate signal, a cumulative block carry generate signal and a carry signal to directly generate the real carry signal. The number of elements of the binary operator is greatly reduced without sacrificing the high speed of computation since two presumed sum or carry signals are never generated in parallel.

Binary operator using block select look ahead system which serves as

An operation circuit for M-bits parallel full addition includes partitioned adders and first and second multiplexers. Each of the first multiplexers selects one of paired provisional carry signals C.sub.ns-1 (1) and C.sub.ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C.sub.(s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C.sub.ns-1 to be progatatd from the s-th partitioned adder. Each of the second multiplexers generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k=n(s+1)-1, n(s+2) -1, . . . , n(s+l)-1) by referring to paired provisional carry signals Cr(1) (or Cr*(1); r=k-n=ns-1) and Cr(0) (or Cr*(0); k-n=ns-1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate l real carry signals Ck at the same time by selecting either the provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C.sub.(s-1)n-1 relating to a digit which is one digit lower than the lowest-order digit of the s-th partitioned adder.

Logic circuit having carry select adders

A carry propagation circuit of a parallel-type full adder having a plurality of bits. The carry propagation circuit includes: a control unit for controlling a carry propagation; a main path including a plurality of transfer circuits serially connected and provided for each of the plurality of bits, each transferring a carry signal from a lower bit to a higher bit when it is brought to an ON state by the control unit; and at least one bypath arranged to bypass a predetermined number of the transfer circuits and brought to an enable state or a disable state by the control unit. When the control unit brings the bypath to the enable state, it brings to the OFF state a transfer circuit provided immediately in the lower bit side of the main path seen from a terminated point of the bypath and thus propagates only a carry signal propagated via the bypath to the higher bit side. This contributes to reducing the propagation delay time required for a carry operation to the minimum and thus realizing a high speed operational processing.

Carry propagation circuit of parallel-type full adder

A masterslice semiconductor device is provided, which reduces or eliminates unused transistors. In the basic cells of the masterslice semiconductor device, each transistor is formed as electrically independent from the others; i.e., each transistor has an individual gate electrode and has an individual region for the source and drain. Terminals formed in parallel to the gate channel of each transistor permits interconnection of the electrodes in a basic cell array using a straight wiring pattern. Such a straight interconnection reduces the effective number of wiring channels needed for a unit cell, and facilitates construction of a larger scale unit cell in a basic cell array.

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Ebina, Japan

Gensuke Goto