Hewlett Packard Enterprise Development LP

Gennadiy Rozenberg

David F Heinrich

Melvin K Benedict

Daniel Humphrey

James Jeffery Schulze

Stewart Gavin Goodson, Ii

Scott P Faasse

Naysen J Robertson

Daniel Ross Gonzales

Mark Rivera

Pranay Mahendra

Jhovel Louie Lopez

Jhovel Louie L Lopez

Stephen Robert Jones

A system is provided, which manages, by a microcontroller internal to a fan installed in a server, power data associated with the fan, wherein the fan includes two pins configured to communicate signals based on an inter-integrated circuit (I2C). During operation of the fan, the microcontroller measures a first and second amount of power consumed by the fan at a first and second time. The microcontroller transmits, via the two pins, the information to a system management entity which monitors and manages the server, wherein the system management entity controls a speed of the fan in response to receiving the measured power data and based on a net power comprising a difference between a total amount of power consumed by the server and an amount of power consumed by the fan.

Fan enhancements to improve server performance and quality

A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.

Communicating management traffic between baseboard management controllers and network interface controllers

A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image. The MR also comprises PLD authentication instructions which, when executed by the management processor, cause the management processor to retrieve an address for the PLD configuration image from the PLD via the management interface, use the address to retrieve the PLD configuration image from the PLD via the management interface, retrieve the cryptographic signature from the PLD via the management interface, and use the cryptographic signature and a cryptographic key of a trusted entity to authenticate the PLD configuration image.

Verification of programmable logic devices

In some examples, an Emergency Power Off (EPO) device can be connected to a non-EPO port of a computing device, and the EPO device can provide an EPO signal via the non-EPO port to a manager connected to an energy storage device of the computing device, wherein the EPO signal comprises instructions to power off the energy storage device.

Emergency power off devices

Examples disclosed herein relate to video output instructions to determine whether a pre-boot video signal is to be provided and, in response to determining that the request for the pre-boot video signal has been received, enable power to an auxiliary output and provide the pre-boot video signal to a display device communicatively coupled to the auxiliary output.

Pre-boot video signal

Growing community of inventors

Houston, TX, United States of America

Gennadiy Rozenberg