National Semiconductor Corporation

Gengying Gao

Kevin C Weaver

Hengyang (James) Lin

Mohan Yegnashankaran

In a lapping process for lapping away layers from a semiconductor device, where the region of interest is located near an edge or corner of the device, the method includes adding additional semiconductor material adjacent the region of interest.

Method of parallel lapping a semiconductor die

In a method of testing a 3D packaged IC, the dies are tested under power by mounting on a specifically designed printed circuit board with a window in it for testing the die sequentially from below using a laser beam tester. The die found not to be defective is partially removed in sequential manner to allow the next higher die to be tested. The partial removal of dies is achieved by grinding a window in them using 'ChipUnzip' techniques.

Method of debugging a 3D packaged IC

A method and system for detecting the location of a defect within an integrated circuit (IC). With power applied to the IC via its power supply terminals (VDD, VSS), an infrared (IR) laser light is scanned along the X and Y dimensions of a surface of the IC. Reflected IR light and the IC power supply current are measured and processed using Fourier Transformation computations. Based upon the results of such computations, the Z coordinate is determined that corresponds to the depth of the defect within the IC.

System and method for detecting location of a defective electrical connection within an integrated circuit

A method for non-destructively testing an IC device to determine the ESD performance. A laser beam is used to probe the diffusions of the device. The amount of light absorbed by the diffusions is determined by monitoring the degree to which light is reflected by the device. The amount of reflection is related to the ESD susceptibility of the device in that the greater the amount of reflection, the worse the ESD performance of the device.

Method of testing the electrostatic discharge performance of an IC device

A vibration resistant test module for use with semiconductor device test apparatus that includes a test module top plate, a test module bottom plate and a plurality of spring-and-wire assemblies. The test module top and bottom plates each have a plurality of openings extending between their upper and lower surfaces. Each of the spring-and-wire assemblies includes an electrically conducting wire with a top wire end and a bottom wire end, a top electrically conducting spring connector attached to the top wire end, and a bottom electrically conducting spring connector attached to the bottom wire end. The spring-and-wire assemblies are threaded through separate openings in the test module top and bottom plates such that the top electrically conducting spring connectors extend above the upper surface of the test module top plate, while the bottom electrically conducting spring connectors extend below the lower surface of the test module bottom plate. The top and bottom electrically conducting spring connectors are used to make secure and vibration resistant electrical connections between the vibration resistant test module and other semiconductor device test apparatus components.

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Fremont, CA, United States of America

Gengying Gao