International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Geng Wang

Kangguo Cheng

Chengwen Pei

Juntao Li

Joseph Ervin

Ravi Mahendra Todi

Qintao Zhang

Roger Allen Booth, Jr

Paul Christian Parries

Yanli Zhang

Herbert Lei Ho

Ramachandra Divakaruni

Xiangdong Chen

Carl John Radens

Jeffrey Bowman Johnson

Karen A Nummy

Jack Allan Mandelman

Kevin McStay

Dureseti Chidambarrao

Subramanian Srikanteswara Iyer

Byeong Yeol Kim

David Michael Fried

Sang Won Lee

Naoyoshi Kusaba

Huilong Zhu

John Edward Barth, Jr

Oh-Jung Kwon

Xi Li

Yujun Li

Junedong Lee

Gan Wang

Hoki Kim

Ali Khakifirooz

Haining S Yang

Hemanth Jagannathan

Sivananda K Kanakasabapathy

Shreesh Narasimha

Babar Ali Khan

Qiqing Christine Ouyang

Abhishek Dube

Gregory Gower Freeman

Werner A Rausch

Michael Sperling

Gerd Pfeiffer

Kam Leung Lee

Brian W Messenger

Katsunori Onishi

Keung Youn Cho

Zhaohui Li

Bruce Bennett Doris

Jeffrey P Gambino

Michael Patrick Chudzik

Chandrasekharan Kothandaraman

Sami Rosenblatt

Thomas W Dyer

Pranita Kulkarni

Robert C Wong

Johnathan E Faltermeier

Michael P Belyansky

Robert Hannon

Hyung Jai Lee

Edward P Maciejewski

Da Zhang

Mary Elizabeth Weybright

Bidan Zhang

Hae Jung Lee

Ravi K Dasaka

Roger A Booth

Ahmed Nayaz Noemaun

Yujun c/o Ibm United Kingdom Ltd Li

A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Vertical field effect transistor including integrated antifuse

An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches.

Inductor with ferromagnetic cores

A method of making an inductor includes forming a plurality of first metal layers on a substrate and an ILD. The method includes patterning a plurality of trenches in the ILD, depositing a magnetic material, and depositing another layer of ILD. The method further includes patterning a plurality of vias adjacent to the trenches filled with the magnetic material, and patterning trenches in the another layer of ILD. The trenches in the another layer of ILD include first portions arranged over, adjacent to and substantially parallel the plurality of first metal layers, and the second portions arranged substantially perpendicular to the first portions, extending from both ends of the first portions, and oriented in opposite directions such that the second portions are continuous with the plurality of vias. The method includes depositing a metal in the plurality of vias and the trenches in the another layer of ILD.

Manufacturing method for inductor with ferromagnetic cores

A semiconductor device having transistors and anti-fuses integrated thereon includes a transistor region having a defect free monocrystalline semiconductor layer and a device channel for a transistor. The device also has an anti-fuse region including a defective semiconductor layer formed on an oxide of a portion of the surface of an epitaxial semiconductor layer over which the transistor is formed, the oxide having a thickness extending into the epitaxial semiconductor layer. It also has gate structures formed in the transistor region and in the anti-fuse region, where the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.

Anti-fuse with reduced programming voltage

A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Metal trench capacitor and improved isolation and methods of manufacture

Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

Integrated LDMOS and VFET transistors

The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.

Programmable device compatible with vertical transistor flow

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

A method of making an inductor device includes forming a first metal layer and an ILD on a substrate, patterning a trench perpendicular to the first metal layer in the ILD, and depositing a magnetic material. The method includes depositing another ILD and patterning a via adjacent to the trench that extends from the first metal layer to a surface of the ILD. The method includes patterning trenches in the ILD, with a first portion over and adjacent to and parallel to the first metal layer, and a second portion perpendicular to the first portion and extending from an end of the first portion to the via. The first metal layer and trenches are connected to through the via. The method includes depositing a metal in the via, and depositing a metal in the trenches to form a second metal layer connected to the first metal layer through the via.

Method of manufacturing inductor with ferromagnetic cores

Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.

High density nanosheet diodes

The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

Electrical and optical via connections on a same chip

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Nanosheet transistors having different gate dielectric thicknesses on the same chip

Growing community of inventors

Stormville, NY, United States of America

Geng Wang