International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Samsung Electronics Co., Ltd.

Geng Han

Lars W Liebmann

Scott Marshall Mansfield

Dongbing Shao

Ruilong Xie

Daniel Chanemougame

Ioana C Graur

Wai-Kin Li

Xu Ouyang

Daniel James Dechene

Ramya Viswanathan

Sang Yil Chang

Guillaume Bouche

Yunpeng Yin

Rasit Onur Topaloglu

Stuart A Sieg

Fook-Luen Heng

Rama Nand Singh

Allen H Gabor

Lei Sun

Michael E Scaman

Jia Zeng

Dario Gil

Donald J Samuels

William Harrington Brearley

Jason E Meiring

Jin Fuw Lee

Dominique L Nguyen-Ngoc

Yuping Cui

Chao Yi Tien, Legal Representative

Scott M Mansfiled

Method and apparatus for improved and efficient spacer assisted lithography-etch-lithography etch (SALELE) processes that utilize a spin-on-material layer, where the spin-on-material layer fills gaps between spacers to protect line-end to line-end spaces created by a cut shape. The method and structures also include a final resist layer with varying critical dimensions (CDs). The use of the spin-on-material enables back end of line (BEOL) metal designs with continuous line-end to line-end spacing above a minimum that can be patterned with a cut mask and spacer only process.

Method for forming continuous line-end to line-end spaces with spacer assisted lithography-etch-lithography etch processes

An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

Metallization lines on integrated circuit products

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Addressing layout retargeting shortfalls

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

Hybrid optical and EUV lithography

A method for semiconductor structure design includes performing, by a processor, error processing of an initial design file layout. The processor further detects a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the T2T structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure.

Structure design generation for fixing metal tip-to-tip across cell boundary

An apparatus including a memory storing instructions and a processor executing the instructions to perform a method including: performing error processing of an initial design file layout; detecting a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules; retargeting the Vx for generating a resulting design file layout of the semiconductor structure; and generating a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.

A method for structure design including a processor performing error processing of an initial design file layout. The processor detects a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure. A physical semiconductor structure is generated based on the resulting design file layout of the semiconductor structure.

A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an existing masking layer and thus does not alter the printed image, improves the critical dimension uniformity (CDU) of main critical (non-dummy) features at the same masking level.

Dummy pattern addition to improve CD uniformity

One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate and forming a metallization blocking structure in the layer of insulating material at a location that is in a path of a metallization trench to be formed in the layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material. The method also includes forming the metallization trench in the layer of insulating material on opposite sides of the metallization blocking structure and forming a conductive metallization line in the metallization trench on opposite sides of the metallization blocking structure.

Methods of forming metallization lines on integrated circuit products and the resulting products

A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

Method of simultaneous lithography and etch correction flow

A method for structure design including detecting, by a processor, a tip-to-tip (T2T) structure design violation for a metal layer above (Ma) a via (Vx) at a tip of the Ma for a design file layout for the structure. Upon detection of the T2T structure design violation, retargeting, by the processor, of the Vx based on adjusting of both the Ma and a metal layer (Mb) below the Vx that connects the Ma through the Vx for the design file layout of the structure to improve performance of the structure based on fixing metal tip or metal ending across cell boundaries.

In an approach for predicting a process fail limit for a semiconductor manufacturing process, a computer determines a potential working process condition for each of a plurality of process parameters varied in forming a test wafer feature. The computer determines a process sigma value for each of the plurality of process parameters in forming the test wafer feature and a measurement sigma value. The computer evaluates a set of measurements of the test wafer feature compared to an acceptable wafer feature dimension, where each measurement of the set of measurements is a pass or fail as compared to the acceptable wafer feature dimension. The computer determines whether one or more fails are evaluated compared to the acceptable wafer feature dimension. The computer produces a predicted process fail limit based, at least in part, on the evaluation of fails, the measurement sigma value, and a desired target sigma value.

Predicting process fail limits

A method of fabricating a semiconductor device includes forming a masking layer on an upper surface of a semiconductor substrate. The masking layer is patterned to form at least one masking element that designates an active region of the semiconductor substrate and at least one patterning assist feature adjacent the at least one masking element. An etching process is performed to form a plurality of semiconductor fins on the semiconductor substrate. The plurality of semiconductor fins include at least one isolated fin formed on the active region according to the at least one masking element and at least one sacrificial fin formed according to the patterning assist feature that reduces a loading effect that occurs during the etching process.

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Fishkill, NY, United States of America

Geng Han