Nuvoton Technology Corporation

Gene Sheu

Po-An Chen

Shao-Ming Yang

Vivek Ningaraju

Md Imran Siddiqui

Subramanya Jayasheela Rao

Syed Neyaz Imam

Shaik Mastanbasheer

Aanand

Pooja Ravindra Deshmane

Syed Sarwar Imam

Antonius Fran Yannu Pramudyo

Monika Bharti

Erry Dwi Kurniawan

Abijith Prakash

Jung-Ruey Tsai

A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high-voltage well region disposed in the semiconductor substrate and having a second conductivity type that is opposite to the first conductivity type. The high-voltage semiconductor device also includes a first buried layer disposed on the first high-voltage well region and having the first conductivity type, and a second buried layer and a third buried layer disposed on the first high-voltage well region and having the second conductivity type, wherein the first buried layer is between the second buried layer and the third buried layer. The high-voltage semiconductor device further includes a source region and a drain region disposed on the first buried layer and having the second conductivity type.

High-voltage semiconductor devices and methods for manufacturing the same

A PIN diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate. The PIN diode includes a semiconductor layer, disposed on the insulating structure. The semiconductor layer includes a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one intrinsic region without being doped or lightly doped between the first doped region and the at least one second doped region. The first conductive type is opposite to the second conductivity type. At least one interconnection structure is disposed on the insulating structure to electrically connect the at least one intrinsic region to the high voltage doped well.

High voltage PIN diode

A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well.

Semiconductor device

A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region.

Semiconductor device and method of fabricating the same

A metal oxide semiconductor field transistor including a gate electrode, a gate dielectric layer, a source region, a drain region, and a top doped region are provided. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounded the drain region. The gate electrode is located above the substrate between the source region and the drain region. The gate dielectric layer is located between the gate electrode and the substrate. The top doped region of a second conductivity type is located in the substrate between the gate electrode and the drain region. The top doped region includes at least three regions. Each of the three regions has a dopant concentration gradient and a concentration gradually decreased from a region adjacent the gate electrode to a region adjacent the drain region.

Metal oxide semiconductor field transistor and method of fabricating the same

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Hsinchu, Taiwan

Gene Sheu