Amdahl Corporation

Trilogy Computer Development Partners, Ltd.

Other

Digital Equipment Corporation

Trilogy Systems Corporation

Gene M Amdahl

James C Lee

Gary A Woffinden

Richard L Beck

Donald L Hanson

Carlton G Amdahl

Hsiao-Peng S Lee

John William Sliwa

Ronald K Kreuzenstein

Stephen J Rawlinson

Chune Lee

Edward Hu

Andrzej Kucharek

Robert J Beall

Robert M Reinschmidt

Gwynne L Roshon-Larsen

Stephen F Stuart

Jerzy R Sochor

Robert F Quinn

Anthony Matouk

A multiple chip self-aligning clock distribution system. The clock signal provided to any given chip is delayed by the on-chip distribution time of every other chip with which it is to be synchronized. Equal delay paths are added to each chip which provide a delay equal to the clock distribution delay of the chip. The equal delay paths can comprise a series of logic gates, such as for example inverters. The clock distribution delay of the equal delay path is designed to be equal to the clock distribution delay of the clock distribution tree on the chip. For each chip to be synchronized, the clock signal is routed through an equal delay path on each of the other chips to be synchronized before being coupled to the clock distribution input terminal of the destination chip. The number of equal delay paths that is included on each chip is a function of the number of chips to be synchronized. 'N' equal delay paths are used where the number of chips is greater than 2.sup.N-1 and is less than or equal to 2.sup.N. Process variations that affect the clock distribution delay of the logic on the chip are likely to have a similar effect on the clock distribution delay of the equal delay path. This minimizes the effect of process variations on the clock alignment in the system.

System and method for multiple chip self-aligning clock distribution

A new class of shift registers that shift the contents of a 2.sup.n bit length register up to 2.sup.n -1 positions in n cycles. Shift registers according to the present invention can be constructed to shift left, shift right, or to shift either left or right. A general implementation of this class of shift registers comprises the following hardware: 2.sup.n D flip-flops or D latches for the data register positions of the shift register; logic for each of the 2.sup.n positions to determine the input value to which the position should take on at each of the n cycles; an n bit shift count register to store a value indicating the number of positions to shift; control lines specifying whether to shift left or right; n control lines which are sequentially raised for one cycle to select a bit in the shift count register for the current cycle beginning with the most significant bit and continuing sequentially to the least significant bit; and a clock to set the selected input data to each position in the shift register.

Method and apparatus for a logarithmic shift register

A semiconductor mounting system is provided for the detachable surface mounting of one or more semiconductor dies on a conductor substrate, such as a ceramic substrate or printed circuit board. The system employs a resilient, anisotropic conductor pad which is interposed between the semiconductor die and the conductor substrate. The conductor pad is capable of conducting electric signals in one direction only, and insulates in the other two orthogonal directions. Thus, by compressing the semiconductor die and resilient conductor pad against the conductor substrate, electrical contact is established between contacts on the semiconductor die and corresponding contacts on the conductor substrate. In the preferred embodiment, additional conductor pads are placed over the semiconductor dies, and a heat sink placed over the second conductor pads. In this way, the semiconductor dies are mounted in a resilient structure for protection, while heat dissipation is enhanced by the metallic elements in the second conductor pad.

System for detachably mounting semiconductors on conductor substrate

A semiconductor chip module for a semiconductor chip having an exposed front face with a two dimensional array of contacts is disclosed. A connector plate is located proximate the front face of the chip. The connector plate has a plurality of apertures which correspond to and are aligned with the contacts of the semiconductor chip. A plurality of transmission elements are located proximate the connector plate opposite from the semiconductor chip. A plurality of flexible conductors extend through the respective apertures of the connector plate. The flexible conductors are electrically coupled to the contacts of the chip and to the transmission elements.

Semiconductor chip interface

A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.

Semiconductor chip module interconnection system

A memory system which comprises a mainstore for storing lines of data and a buffer store for storing lines of data that are a subset of the data stored in the main store. The buffer store is comprised of a plurality of associativities. A line of data stored in the buffer having a given address may be stored in any one of the plurality of associativities. A tag store stores a tag for the associativities. A field from a buffer store address is compared with the stored tag in the tag store to produce a data selection signal for selecting from among the plurality of associativities the proper line of data. When the buffer has only two associativities, a bit in the buffer store address which has different values for the two associativities is tested, and thus the proper line of data is selected. The bit position is indicated by a pointer stored in the tag array. A selection of one of two data lines is made prior to a determination of the presence or validity of data in the buffer store.

Addressing system for an associative cache memory

A circuit structure, and method for forming the structure, permits wafer scale integration by fabricating plural copies of the circuit in integrated circuit form, and interconnecting predetermined circuit element groups of the copies in a manner that permits a majority voting operation to take place. In this manner, defective circuit elements are masked by being out-voted by corresponding non-defective circuit elements that participate in the voting process. Alternate embodiments of a voter unit, used to implement the voting operation, includes a preferred embodiment that takes advantage of emitter-coupled-logic structure to provide a multiplex, voter, latch combination capable of selectively implementing normal and diagnostic operation. Included in the preferred embodiment of the voter unit is a fused link that implements a repair operation in the event there exists more defective circuit element groups than non-defective circuit element groups participating in the voting process.

Integrated circuit redundancy and method for achieving high-yield

Disclosed is a data processing system including virtual-addressed and real-addressed stores. One store is addressed with real addresses and the other store is addressed with virtual addresses. Whenever an addressed location is to be accessed in a store addressed by the other type of addresses, the address is translated to the other type of address. If a virtual address cannot access the desired location in the virtual store, the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real store. Whenever a real address needs to access a virtual address location in the virtual-addressed store, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory.

Virtually addressed cache

A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic. A plurality of connectors emanate from the ceramic and are electrically coupled by vias or traces through the ceramic to the signal contacts for the transmission of signals to and from the chip.

Module construction for semiconductor chip

A sequencing apparatus and method employing two or more control stores for use within a data processing system. Where two-way branching exists, first and second control stores each provide control words for the common control of units within a data processing system. Whenever a branch is specified, a corresponding branch address is provided in the first control store for addressing the second control store. A nonbranch address is provided for addressing the first control store. The nonbranch address and the branch address each are employed to access concurrently control words from the first and second control stores. Upon the determination of the state of the branch condition, the appropriate one of the previously accessed control words is selected without delay and without need for an additional cycle to access the control stores.

Multiple module control store for use in a data processing system

Disclosed is a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system. An operand comparator includes one or more half-adders to predict carry outs at an early time. The comparator is used in a data processing system which is operative in response to instructions having operation codes for specifying operations to be executed. The instructions also have operand fields for identifying operands to be utilized in connection with executing the instructions.

Code determination using half-adder based operand comparator

Disclosed is an apparatus for storing data wherein there are at least two storage units which are addressed by different addressing schemes. The primary storage unit is addressed with a unique addressing scheme while the other storage units are addressed with a scheme wherein more than one of the other addresses may map to a single unique primary address. The apparatus for storing data includes a mechanism for translating all of the unique primary addresses to all of the other addresses which map to that unique primary address.

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Atherton, CA, United States of America

Gene M Amdahl