Benchmarq Microelectronics, Inc.

Texas Instruments Corporation

Benchmarg Microelectronics, Inc.

Gene L Armstrong, Ii

David L Freeman

Wallace E Matthews

William F Davies, Jr

David Louis Freeman

A battery monitoring/control device includes a monitor/control device ( ) that is operable to be integrated with a microprocessor system. The system includes a CPU ( ) that interfaces with a data bus ( ) and an address bus ( ). The CPU ( ) interfaces through a data line ( ) with the control/monitor device ( ) and control lines ( ) and ( ). Commands and data can be input to the control/monitor circuit ( ) and data received therefrom. The control/monitor device ( ) includes a controller/data register block ( ) and a battery charge control/monitor block ( ). The device ( ) is operable to monitor the battery voltage of a secondary battery ( ) during charging thereof and to control the rate of charge through a transistor ( ). The battery monitor ( ) determines when the voltage on the battery ( ) reaches a predetermined level indicating full-charge. A discharge circuit ( ) controls a discharge transistor ( ) to discharge the battery ( ) through a sense resistor ( ) for conditioning of the battery. The system receives current from the battery ( ) through the resistor ( ), the current monitored by a Gas Gauge monitor ( ). The Gas Gauge monitor ( ) maintains a measurement of the capacity of the battery ( ). Control and status information is maintained in control/status register ( ), which are set to a default value in a default register ( ) upon power up. The CPU ( ) can store control information in the registers ( ) in order to control the device ( ). Further, status information of the device ( ) can be stored in the register ( ) for access by the CPU ( ) through a bus interface ( ).

System for charging monitoring batteries for a microprocessor based method

A reconfigurable integrated circuit chip includes an output terminal (42) which is connected to the output of an inverting amplifier (44). The integrated circuit chip (10) includes an output terminal (46) which is connected to one input of a comparator (22). The other end of comparator (22) is connected to an internal voltage reference device (48). The output of comparator (22) is connected to the input of the inverting amplifier (44). The integrated circuit chip (10) may be configured as a linear regulator when a transconductance device (14) is connected between a DC power supply (12) and a load and an integrator (24) is connected between terminal (42) and the control input of the transconductance device (14). The integrated circuit chip (10) is configured as a switching regulator when a gated switch (14) is connected between a DC power supply (12) and a switching node (65) wherein the gated switch (14) is gated by the signal output by the output terminal (42). The switching node (65) is connected to the cathode of a switching diode (66) and to one side of a switching inductance (68) with the other side of the switching inductance connected to the load 16. A voltage is sensed across a load resistor (18) and input into the comparator (22) which compares the sensed voltage to the reference voltage (48) and outputs the differential into the output terminal (42). This then controls transistor (14) and causes it to vary the current passing through the load (16).

Linear slewing regulator

A reconfigurable integrated circuit chip includes an output terminal (42) which is connected to the output of an inverting amplifier (44). The integrated circuit chip (10) includes an output terminal (46) which is connected to one input of a comparator (22). The other end of comparator (22) is connected to an internal voltage reference device (48). The output of comparator (22) is connected to the input of the inverting amplifier (44). The integrated circuit chip (10) may be configured as a linear regulator when a transconductance device (14) is connected between a DC power supply (12) and a load and an integrator (24) is connected between terminal (42) and the control input of the transconductance device (14). The integrated circuit chip (10) is configured as a switching regulator when a gated switch (14) is connected between a DC power supply (12) and a switching node (65) wherein the gated switch (14) is gated by the signal output by the output terminal (42). The switching node (65) is connected to the cathode of a switching diode (66) and to one side of a switching inductance (68) with the other side of the switching inductance connected to the load 16. A voltage is sensed across a load resistor (18) and input into the comparator (22) which compares the sensed voltage to the reference voltage (48) and outputs the differential waveform into the output terminal (42). This then controls transistor (14) and causes it to vary the current passing through the load (16).

Linear/switching regulator circuit

A battery monitoring/control device includes a monitor/control device (35) that is operable to be integrated with a microprocessor system. The system includes a CPU (12) that interfaces with a data bus (14) and an address bus (16). The CPU (12) interfaces through a data line (40) with the control/monitor device (35) and control lines (28) and (34). Commands and data can be input to the control/monitor circuit (35) and data received therefrom. The control/monitor device (35) includes a controller/data register block (36) and a battery charge control/monitor block (44). The device (35) is operable to monitor the battery voltage of a secondary battery (46) during charging thereof and to control the rate of charge through a transistor (66). The battery monitor (90) determines when the voltage on the battery (46) reaches a predetermined level indicating full-charge. A discharge circuit (94) controls a discharge transistor (72) to discharge the battery (46) through a sense resistor (68) for conditioning of the battery. The system receives current from the battery (46) through the resistor (68), the current monitored by a Gas Gauge monitor (92). The Gas Gauge monitor (92) maintains a measurement of the capacity of the battery (46). Control and status information is maintained in control/status register (56), which are set to a default value in a default register (57) upon power up. The CPU (12) can store control information in the registers (56) in order to control the device (35). Further, status information of the device (35) can be stored in the register (56) for access by the CPU (12) through a bus interface (52).

System for charging/monitoring batteries for a microprocessor based

The low power voltage comparator with hysteresis includes a comparator (10) that is operable to receive the output from a battery (14) on the positive input thereof and the output of a battery (16) on the negative input thereof. An offset circuit (22) is provided in series with the voltage of the battery (14) and the comparator (10), and an offset circuit (24) is provided between the battery (16) and the comparator (10). The offset circuits (22) and (24) are adjustable by a hysteresis control circuit (26) to offset the voltage thereof for the non-selected battery to be higher than that for the selected battery such that the voltage drop across the offset for the non-selected battery is greater than that for the selected battery. When the voltage on the selected battery falls below the offset voltage of the non-selected battery, the hysteresis control then decreases the offset upon selecting the other battery and increases the offset or the battery that is deselected. The offset circuits (22) and (24) each comprise primary resistive elements (26) and (36) which are connected through a current sink (50) to ground. The selection process by the hysteresis control circuit (26) is operable to place a parallel resistor (32) or (44) in parallel with the resistors (26) and (36), respectively. The selection process is effected with switches (34) and (46).

Low-power semiconductor voltage comparator with hysteresis

A fuse state sense circuit includes a fusible link (40) that is disposed between a node (38) and ground. A programming/sense pad (42) is provided to allow voltage to be applied to the node (38) external to the fuse state sense circuit. Current is provided to the node (38) through a current source (30) and a transistor (36). The transistor (36) is controlled by a bias current. An output node (32) is disposed between the current source (30) and the transistor (36). This is connected to the output through an inverter (34). In operation, the voltage on node (38) is raised to a first level to turn off transistor (36) to allow the output to be exercised and to change the state thereof to emulate the fusible link (40) being open. In a second and programming mode, the voltage on the node (38) is raised to a much higher level to allow sufficient current to flow through fusible link (40) to open it. Transistor ( 36) in this mode is rendered non-conductive and isolates the node (38) from the remaining portion of the circuit.

Fuse state sense circuit

A three-state input circuit operable to sense three separate logic states on an input pad (10) is operable to sense whether the current is sourced to the pad from a positive source or sinked from the pad to a negative source to provide two logic states. A third logic state is provided when it is determined that current is not being sourced to or sinked from the pad (10). A current source (36) is connected from a positive rail (14) through the source/drain path of an N-channel transistor (40) to the pad (10). This provides a sink current comparator function. A source current comparator function is provided by a current source (42) that is connected to the pad (10) through the source/drain path of a P-channel transistor (46) and to a negative voltage rail (18). The transistor (40) has a first bias voltage V.sub.B1 connected to the gate thereof and the transistor (46) has a second bias voltage V.sub.B2 connected to the gate thereof. When the pad (10) is connected to the negative rail (18) to sink current from the pad (10), current is conducted through the source/drain path of transistor (40). This is sensed by a decision logic circuit (32) to determine the first logic state. When current is sourced to the pad (10) from the positive rail (14), the transistor (46) turns on and current is passed through the current source (42) to represent a second logic state. When current is not sourced to or sinked from the pad (10) from an external positive or negative voltage source, both transistor (40) and transistor (46) are off, representing a third logic state.

Three state input circuit for an integrated circuit

A power resource management system includes a battery charging system (20) that is connected between a positive voltage terminal and a voltage sense terminal (15). An operating system (10), that in one mode operates off of the battery and in a second and charging mode operates off the power source (24), is connected between the positive terminal (12) and the voltage sense node (15). A sense resistor (16) is connected between the voltage sense node (15) and a ground terminal (18). The power source (24) is operable to deliver voltage across the positive terminal (12) and the negative terminal (18). The battery charger (20) includes a charge modulator (24) and a buck regulator which has a switch (26) that is controlled by the controller (34). The controller (34) receives the voltage on the node (15) and controls the switch (26) in accordance with the voltage thereon, which voltage is a function of both the current supplied to the operating system ( 10) and the current supplied to the battery (22) for a charging operation. As the operating system current increases, the charge delivered to the battery decreases and, conversely, as the current to the operating system (10) decreases, the current delivered to a battery (22) increases.

Power resource management system

A differential comparator is provided for controlling two switches (40) and (42) to switch two supplies (10) and (12), respectively, to a common output node (22). The decision/control circuit (44) outputs two control signals (46) and (48), the logic state thereof being a function of whether supply (10) is higher than supply (12) or supply (12) is higher than supply (10). The operating power for the decision/control circuit (44) is derived from the supplies (10) and (12), and not from the common output node (22), such that when the switches (40) and (42) are closed and no power is being supplied by either of the supplies (10) and (12), the decision/control circuit (44) has sufficient power to make a decision.

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Garland, TX, United States of America

Gene L Armstrong, Ii