Cisco Technology, Inc.

Integrated Device Technology, Inc.

Zettacom, Inc.

Gene K Chui

Matthew D Ornes

Christopher I W Norrie

Eugene T Wang

Onchuen (Daryn) Lau

Lambert Fong

Gary Kipnis

Gurmohan Singh Samrao

Frank Chui

Robert James Divivier

Onchuen D Lau

King-Shing (Frank) Chui

Chris D Bergen

Chris Norrie

Neil King

David Anthony Hughes

Madhav V Marathe

Lionel A King

Dan Klausmeier

Daryn Lau

O Daryn Lau

Gurmobau Samrao

A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N&#xd7;N' switch matrix is programmably made to operate as if it were a plurality of S&#xd7;S&#x2032; virtual switch slices, where S&#x3c;N and S&#x2032;&#x3c;N&#x2032;. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for. An inventory of PSSU's may be distributed in accordance with the disclosure to segmented markets such that each PSSU can service the specific needs of a market, be it providing a plurality of 4&#xd7;4 switch slices, 8&#xd7;8 switch slices, 16&#xd7;16 switch slices, or otherwise. In one embodiment, virtual slices are distributed throughout a physical switch-matrix so as to minimize pinout crossover for external line card units.

Programmably sliceable switch-fabric unit and methods of use

A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.

Method and system for error correction over serial link

In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits

A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.

Multiservice switching system with distributed switch fabric

A method and apparatus for scheduling static and dynamic traffic through a switch fabric are described. The method comprises for each switch slice in a distributed switch fabric, scheduling static traffic by reserving time slots for transmission of the static traffic to at least one destination, and scheduling dynamic traffic so as not to be transmitting the dynamic traffic to the at least one destination during the reserved time slots. The apparatus implements the method and comprises a memory storing a schedule of static traffic, shifters storing dynamic traffic scheduling requests, and a grant scheduler.

Method and apparatus for scheduling static and dynamic traffic through a switch fabric

An apparatus and method for reordering sequence indicated information units into proper sequence are described. The apparatus includes a double-back shifter receiving sequence indicated information units, and at least one circuit coupled to the double-back shifter to repetitively compare, reorder and shift the sequence indicated information units so as to be in proper sequence when shifted out of the double-back shifter. The method includes repetitively comparing, reordering and shifting sequence indicated information units in a double-back shifter so as to be in proper sequence when shifted out of the double-back shifter.

Apparatus and method for reordering sequence indicated information units into proper sequence

A method and apparatus for providing programmable memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprise asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at least one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface. The first unidirectional FIFO buffer is coupled to read at least one cell to at least one switch, and the second unidirectional FIFO buffer is coupled to write at least one cell from at least one switch, wherein the switch handles cells from sources having a number of bandwidths. The switch is coupled to route the at least one cell between an OC12 trunk line and at least one service module. The service module is coupled to provide the cell to at least one service subscriber using T1, E1, T3, E3, OC3, and OC 12 ports.

Method and apparatus for providing programmable memory functions for bi-directional traffic in a switch platform

A synchronization state for a local clock generating circuit of a first of a number of components of a distributed system is maintained according to a number of local clock cycles recorded between successive occurrences of a global synchronization signal provided to the components within the distributed system. The local clock generating circuit may enters the synchronization state only after observing a predetermined number of occurrences of successive local clock cycles between instances of the global synchronization signal. The local clock generating circuit continues to provide local control signals for the first of the components at time instants corresponding to the number of local clock cycles even after an instance of the global synchronization signal is observed at a time instant corresponding to one local clock cycle more or less than the number of local clock cycles. However, the local clock generating circuit enters an alarm state when the global synchronization signal is observed at time instants corresponding to more than one local clock cycle more or less than the number of local clock cycles.

Scheme for maintaining synchronization in an inherently asynchronous system

An apparatus is described comprising an ingress port and a plurality of switch planes where each of the switch planes has a dedicated scheduler and each of the switch planes are communicatively coupled to the ingress port. The switch planes may further have at least one input control port and at least one output control port where each of the input control ports are coupled to each of the output control ports in a crossbar arrangement. The communicative coupling may further comprise one of the input control ports coupled to the ingress port. Furthermore, the ingress port may have at least one unicast queue which is dedicated to a specific egress port. The ingress port may also have a multicast queue. The dedicated scheduler may further comprise a pointer to determine priority between multicast and unicast traffic, a pointer to determine priority between contending input control ports having multicast traffic and/or a pointer for each of the output control ports to determine priority between contending input control ports having unicast traffic. The apparatus may also further comprise a plurality of ingress ports where each of the ingress ports are communicatively coupled to one of each of the input control ports.

Crosspoint switch with independent schedulers

A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data that is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verify the integrity of the transmitted ECC code itself.

A method of managing a network switch. The method having the first step of detecting a status of a set of physical ports on an interface card in the network switch. Then, determining if the status is in a first state that indicates that all physical ports in the interface card are inaccessible. If the status is in the first state, then accepting all traffic for the set of physical ports. Also disclosed is an apparatus for performing the method.

Method and apparatus of handling data that is sent to non-existent destinations

An apparatus and method for reducing congestion in a network switching node. A congestion mask that indicates which of a plurality of destination ports in a network switching node are congested is generated and combined with a destination port field included in a packet in a multicast queue of the switching node to mask destination port designations in the destination port field that are indicated by the congestion mask to be congested if a drop eligibility field within the packet indicates that destination port designations are permitted to be masked. The packet is dequeued from the multicast queue to be forwarded to destination ports in the network switching node indicated by destination port designations in the destination port field not masked by the combination of the congestion mask with the destination port field.

Dynamically delisting and relisting multicast destinations in a network switching node

A communication interface is described to align at a destination data transmitted through different channels before that data is read out. The communication interface includes a receiver circuit that has a plurality of buffers. Each buffer is coupled to a corresponding channel to receive data therethrough. The communication interface also includes a control circuit, coupled to the plurality of buffers, to enable reading of data from the plurality of buffers when each of the plurality of buffers has received at least one unit of data.

FIFO buffers receiving data from different serial links and removing unit of data from each buffer based on previous calcuations accounting for trace length differences

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Campbell, CA, United States of America

Gene K Chui