International Business Machines Corporation

Gene J Gaudenzi

Hormazdyar M Dalal

Kenneth Michael Fallon

Georges Henri Robert

Susan L Tempest

Frederic Robert Pierre

Kevin G Kramer

Dennis C Reedy

Joseph M Mosley

Mark A Takacs

Rebecca Yung Gorrell

Kenneth J Travis, Jr

Alexis Bitaillou

Kenneth Robert Herman

Daryl Carvis Cromer

Mark Edward Dean

Patrick M Bland

Helmut Schettler

Giulio DiGiacomo

Nghia Van Phan

Cynthia Susan Milkovich

Perwaiz Nihal

Timothy J Louie

Herve L Beranger

John C Milliken

Vito J Tuozzolo

Maurizio Arienzo

John P Norsworthy

Anthony J Abrami

Alfred F Favata

Kristen A Hausman

Paul C King

Paul V McLaughlin

A multi-level package, and method for making same, that offers a small size with compartmentalized areas that allow for radiation shielding is disclosed. In its simplest embodiment, the invention comprises two cards and an interposer interposed between the two cards. The interposer preferably has an opening, and the combination of the interposer's opening and the two cards form a cavity. The cavity allows for a high amount of components to be packed into a small, three-dimensional space. The interposer supports can act like a Faraday shield. The two cards and interposer can be multi-layered and support any type of chip or package connection on each side of each card or interposer, including through-hole, surface mount, and direct-chip attachment connections. Finally, pick-up plates or heat sinks can be attached to the package.

Multi-level electronic package and method for making same

A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.

Method for forming reflowed solder ball with low melting point metal cap

A capacitor having a multilevel interconnection technology and process thereof. Also disclosed is a process of electrically connecting a capacitor to an object, comprising the steps of first obtaining a capacitor. At least one solder ball is reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contacting means. On this reflowed solder ball a cap of low melting point metal is secured. This can be done in a number of ways. The preferred way is to positioning a mask over the solder ball such that a portion of the solder ball is exposed through openings in the mask. At least one layer of a low melting point metal is deposited on the exposed surface of the solder ball through the mask, and thereby forming a capacitor with a multilevel interconnect cap. The low melting point metal can interact with the surface of the solder ball to form a cap of an eutectic or a liquefied portion. The cap portion can then be joined to the object.

Process of forming a capacitor with multi-level interconnection technology

Reflowed solder ball with low melting point metal cap

A material deposition process is disclosed in which apertures of a contact mask used therein have a constricted opening terminating in a `knife edge` in a sidewall thereof near the top mask side, especially within the top 25% of the mask thickness above the substrate. A process is disclosed in which the mask, in addition, has apertures which have larger dimension lower openings on a bottom side of the mask contacting the substrate than constricted openings near the top side of the mask. Single solder bump and 'bump on bump' over BLM (ball limiting metallurgy) processes are disclosed which utilize such contact mask to reduce the damage and detaching of such features during processing and subsequent handling.

Method for forming features upon a substrate

A material deposition contact mask is disclosed in which apertures formed therein have a larger dimension in lower openings in a bottom side of the mask contacting the substrate than in constricted openings located near the top side of the mask. Apertures of the contact mask have knife edges located within the upper sidewalls thereof, e.g. within the top 25% of the mask thickness above the substrate. A mask is disclosed which, in addition, is thermally compensated to the substrate temperature at which the deposition is performed. Methods for fabricating the mask by differential etching are disclosed.

Selective deposition mask and method for making the same

This invention is directed to a capacitor having a multilevel interconnection technology. At least one solder ball is reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contact. On this reflowed solder ball a cap of low melting point metal is secured. This can be done in a number of ways. The preferred way is to positioning a mask over the solder ball such that a portion of the solder ball is exposed through openings in the mask. At least one layer of a low melting point metal is deposited on the exposed surface of the solder ball through the mask, and thereby forming a capacitor with a multilevel interconnect cap. The low melting point metal can interact with the surface of the solder ball to form a cap of an eutectic or a liquefied portion. The cap portion can then be joined to the object.

Capacitor with multi-level interconnection technology

A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability. IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb--Sn solder balls are employed for joining. These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy. Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.

Method for attaching a flip chip on flexible circuit carrier using chip

A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.

Method for making direct chip attach circuit card

A multi-layer module that has incorporated therein an additional sheet with a heat generating film resistor formed thereon. A temperature responsive controller regulates the film resistor current in order to regulate the temperature at the surface of the module. The invention is applicable to both single chip and multiple chip modules, and for multi-chip modules a plurality of discrete film resistors on a single may be used.

Temperature controlled multi-layer module

An electrical device for logic circuits having a package comprising a combination of controlled collapse electrical interconnections, such as solder balls and pin through-hole conductors, wherein the conductors are disposed outside the perimeter of an inter-array of solder balls, which when a maximum number of solder balls are disposed, the array is circular in shape, so as to provide an increased footprint for the electrical device beyond that, otherwise maximum footprint for solder balls alone, which footprint is otherwise limited in size due to failures which occur in solder balls when solder balls are exposed to thermal and mechanical stress levels at extended distances from the neutral or zero stress point of the array.

Surface mount chip package having an array of solder ball contacts

A low cost Surface Mount Carrier (SMC) for carrying integrated circuit chips mounted thereon. The carrier, or interposer, is a thin-small single layer or, a multi-layer deck of printed circuit board (FR-4) material with at least one direct chip attach (DCA) site for mounting a semiconductor chip. The DCA site has chip bonding pads wherein the integrated circuit chip's pads are wire bonded to or soldered to the carrier. The bonding pads are connected to wiring pads through interlevel vias and wiring lands or traces which may be on one of several wiring planes. The carrier is connected to the next level of packaging through the wiring pads.

Direct chip attach module (DCAM)

An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

ECC function with self-contained high performance partial write or

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

Bidirectional buffer with latch and parity capability

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

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Purdys, NY, United States of America

Gene J Gaudenzi