Intel Corporation

Ncr Corporation

Ncr Corportion

Gene F Young

Larry C James

Roy M Stevens

Craig A Walrath

Edward A McDonald

Thomas F Heil

Jimmy D Pike

Nagabhushan Chitlur

Kevin W Bross

Arthur F Cochcroft, Jr

James M Ottinger

Michael R Hilley

Daniel C Robbins

Dirk Blevins

Todd Langley

Terry S Strickland

P Chris Raeuber

Marti D Miller

James S Kluttz

Frank W Cabaniss

Sudeep Puligundla

Apparatuses and systems associated with expansion card design with a coherent connector to provide for coherent communication are disclosed herein. In embodiments, a circuit card may comprise an integrated circuit (IC), a first connector to couple the IC to a processor of a computer device, the first connector to provide for non-coherent communication between the IC and the processor, and a second connector to couple the IC to the processor, the second connector to provide for coherent communication between the IC and the processor. Other embodiments may be described and/or claimed.

Circuit card with coherent interconnect

An apparatus is described. The apparatus includes a first riser card connected to a first card. The apparatus also includes a second riser card connected to a second card, wherein, the first card's connection to the first riser card and the second card's connection to the second riser card pass through a vertical plane runs parallel to respective surfaces of the first and second riser cards.

Interleaved card/riser connection assembly for compact card integration

Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are 'Owned' and 'Unowned.' The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.

Directory-based coherency system for maintaining coherency in a

A symmetric multiprocessor system constructed from industry standard commodity components together with an advanced dual-ported memory controller. The multiprocessor system comprises a processor bus; up to four Intel Pentium.RTM. Pro processors connected to the processor bus; an I/O bus; a system memory; and a dual-ported memory controller connected to the system memory, the dual ported memory controller having a first port connected to the processor bus to manage processor to system memory transactions and a second port connected to the I/O bus to manage I/O transactions. Furthermore, two such systems can be connected together through a common I/O bus, thereby creating an eight-processor Pentium.RTM. Pro processor SMP system.

Dual-ported memory controller which maintains cache coherency using a

An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories. The system memory contains a system memory line state for each line of memory saved within the system memory, the system memory line state being any one of the group: SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B. Each one of these states is represented by a different two bit code saved with each line of memory in system memory. Additionally, each data cache memory contains a data cache memory line state for each line of memory saved within the data cache memory, the data cache memory line state being any one of the group: MODIFIED, EXCLUSIVE, SHARED, or INVALID.

Directory-based coherency system using two bits to maintain coherency on

A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time. The state cache can be a direct mapped cache wherein state information for an associated line of memory is stored within the state cache together with a tag field being a first portion of the address of the associated line of memory, and indexed within the state cache by the remaining portion of the address.

Method and apparatus for caching state information within a

An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories. The method for performing state cache line replacement operations includes the steps of: establishing a default system memory line state of SHARED for lines of memory represented in said state cache memory; reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory; and performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED. Since most lines of memory are in a shared state prior to replacement, setting the default state to a shared state, rather than a uncached state, reduces the number of invalidate coherency operations which must be performed during state cache line replacements.

Method for reducing the number of coherency cycles within a

A dual AC input module providing AC line isolation of different phases without the use of relay control. Power supply load is supported through two AC line feeds, each feed being connected through a bridge rectifier to a common bulk DC power supply backplane. The parallel configuration of AC line feeds and bridge rectifiers eliminates the need for relay control logic to open relays and isolate a failed primary AC line feed prior to closing relays to connect a second AC feed to the power supply, as required with previous dual AC input module designs to isolate different line feeds of different phases.

Dual AC power supply input module

An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.

System for preventing an unselected controller from transferring data

A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.

Retry scheme for controlling transactions between two busses

Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Architectures for computer systems having multiple processors, multiple

In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit. In response to the retry signal, the processor is taken off the system bus and not allowed to regain the system bus until the buffered data is written to main memory. A bus busy signal is raised and will not be lowered until the data is written to main memory. When the busy signal is lowered, the processor regains the system bus and receives an interrupt vector from the interrupt controller. I/O bus ownership is locked until the interrupted processor has received an interrupt vector and the IAK cycle is complete. If no buffered data remains in the interface circuit, no retry signal is generated. The interrupt controller waits a predefined period of time for a retry signal and if none is detected, the interrupt controller issues an appropriate interrupt vector to complete the IAK cycle. For multiple I/O buses, preferably only one interface circuit retries processors issuing IAK cycles.

Method and apparatus for transferring data within a computer system

In a computer, when a block of data is written to memory, it is common to attach a control word to the data. The control word is placed at a pre-arranged location, generally separate from the data. The control word contains important information about the data, such as starting address, length, etc. The presence of the control word indicates that the data is valid. Sometimes, for various reasons, the control word is written before all the data is written. This premature availability of the control word gives false information: the data is not yet completely written, yet the presence of the control word indicates otherwise. The invention prevents such a problem by preventing premature writing of the control word.

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Lexington, SC, United States of America

Gene F Young