Motorola Corporation

Gene A Schriber

Rodney J Means

Harold Garth Nash

Michael F Wiles

Thomas H Bennett

William D Mensch, Jr

Edward C Hepworth

Earl F Carlow

Charles I Peddle

Stanley E Groves

Michael E Spak

Thomas G Gunter

Heinz Bernhard Maeder

Doyle V McAlister

John R Linford

Brian M Spinks

Thomas C Daly

Richard M Baker

Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.

Priority encoder

A high speed, low power clocked driver circuit is provided. DC paths from voltage V.sub.DD to ground is eliminated by carefully clocking field effect transistors within the driver circuit. By using bootstrapping techniques, the output of the circuit approaches V.sub.DD. Two of the high speed, low power driver circuits are combined to drive a ratioless output circuit in order to provide an output buffer circuit having a TTL compatible output.

Driver circuit for use in an output buffer

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.

Interface adaptor architecture

A carrier correction circuit accepts a serial digital data input stream having an underlying carrier frequency associated with it and generates a corrected carrier signal synchronized with the underlying carrier frequency. The input stream may, for example, be a serial output of an analog-to-digital converter having a differential phase shift keyed analog signal applied to its analog input, the underlying carrier frequency being the carrier frequency of the DPSK signal. The carrier correction circuit includes a phase detector which receives the serial digital data input stream and two representations of the recovered carrier which are shifted in phase from each other by 90.degree.. Each of these representations of the recovered carrier is mixed with the serial digital data input stream by means of first and second mixer circuits, and the results are loaded into first and second serial accumulators, which accumulate, respectively, the average products of the two mixer circuits over a certain time period. A magnitude comparator periodically generates an error signal by comparing the magnitudes of the first and second serial accumulators. The carrier correction circuit includes a carrier correction filter which includes an up/down counter which counts up each time the error signal is a '1' and counts down each time it is a '0'. The contents of the up-down counter are averaged to generate a number of correction pulses. A digital controlled oscillator accepts a sign bit and the correction pulses from the carrier correction filter in order to advance or retard the recovered carrier signal to synchronize it with the underlying carrier frequency.

Digital carrier correction circuit

A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch. Reset circuitry resets the counter whenever the 16-bit latch is written into, and the counter counts until it reaches the number written into the 16-bit latch, whereupon the interrupt circuitry generates an interrupt signal and sets an appropriate interrupt bit in the status register, and also resets that counter. The counter continues counting at the appropriate clock rate after the interrupt so that time since the interrupt may be determined by the microprocessor. The outputs of the three counters can be selected as outputs of the programmable timer module.

Programmable timer module coupled to microprocessor system

An MOS input buffer circuit includes an input connected to the gate electrode of an enhancement mode input MOSFET. The drain of the input MOSFET is connected to the output of the input buffer circuit. The source of the input MOSFET is connected to the drain of a second depletion mode MOSFET having its source connected to ground and its gate connected to a V.sub.DD voltage conductor. A load circuit is coupled between the V.sub.DD voltage conductor and the output, and consists of an enhancement mode MOSFET and a depletion load MOSFET coupled in series between output and V.sub.DD voltage conductor. A third depletion mode MOSFET has its drain connected to the V.sub.DD voltage conductor, its source connected to the source of the input MOSFET, and its gate connected to the output. The positive gain (or negative slope) portion of the switching characteristic of the input buffer circuit extends substantially all the way between the high and low output levels.

MOS input buffer with hysteresis

A digital control circuit means responsive to a timing signal and a phase shift control signal accepts digital dibits of data and generates a digital control output signal. A digital phase shifter coupled to the control circuit and responsive to a timing signal generates a main and a secondary channel digital output signal alternately at a first and a second output terminal during successive dibit intervals. The main channel digital output signal is phase shifted a predetermined amount with respect to a main channel digital output signal generated during a preceding dibit interval in response to said digital control output signal. A multiplexer coupled to the first and second output terminals of the phase shifter transmits the main channel digital output signal on a third output terminal and the secondary channel digital output signal on a fourth output terminal. A digital number generator coupled to the third and fourth output terminals and responsive to a timing signal generates a series of digital output signals representative of a predetermined analog magnitude. A digital to analog converter converts the digital output signals from the digital number generator into a differential phase shift keyed analog output signal.

Digital differential phase shift keyed modulator

An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these 'false' outputs eliminates their propagation in the digital system in which said flip-flop is employed.

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Austin, TX, United States of America

Gene A Schriber