International Business Machines Corporation

Gen Yamada

Masatoshi Ishii

Hisatada Miyatake

Paul Marian Harvey

Kazushige Kawasaki

A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Pulse stretching circuit and method

The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b, b, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b, b, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Pulse width adjusting circuit and method

An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are 'floating' in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

Growing community of inventors

Shiga, Japan

Gen Yamada