Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electric Holdings Co., Ltd.

Gen Tada

Akio Kitamura

Naoto Fujishima

Masaru Saito

Yoshihiro Shigeta

Kazuo Matsuzaki

Hideto Kobayashi

Hiroshi Shimabukuro

Masaru Saitou

Takahiro Nomiyama

A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.

Drive device

Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.

Semiconductor integrated circuit for driving the address of a display device

The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.

Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same

The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (N) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the N, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the N. When the input terminal of the semiconductor circuit is at the Hi-level, the NOFF. By connecting the output terminal of the Nto the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the Nis OFF, a desired high voltage is applied between the collector and emitter of the N. Since a p-channel MOSFET (P) is turned ON as the input terminal potential is changed over to the Lo-level and the high voltage is still being applied to the output terminal of the N, the N is turned ON and the Nis brought into the ON-state, in which the current driving ability of the Nis low. The semiconductor circuit can protect the devices from an over voltage with a simple circuit configuration.

Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof

A display device driver circuit includes a timer circuitthat outputs to output stage circuitsa control signal for turning off IGBTsandwhen a next clock signal is not inputted to the timer circuitfor a predetermined period of time, and the output stage circuitsturn off the IGBTsandto put the output terminals Dthereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTsand

Display device driver circuit

A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2&#xd7;10/cmto reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.

Lateral high breakdown voltage MOSFET and device provided therewith

A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2&times;10 /cm to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuing a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.

A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP from the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP , are greater than or equal to lower limit values Mc , Tc . As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.

High withstand voltage semiconductor device

A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.

Semiconductor apparatus and method for manufacturing the same

The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering. The semiconductor device according to the invention includes a p-type highly resistive semiconductor substrate; an n-type offset region in the surface portion of the substrate; a p-type base region in the surface portion of the substrate, the base region including an n -type source region in the surface portion thereof, the base region including a channel portion in the extended portion thereof extended between the source region and the n-type offset region; a p-type offset region in the surface portion of the n-type offset region, the potential of the p-type offset region being fixed at the source potential; an n -type drain region in the surface portion of the n-type offset region; a field oxide film on the p-type offset region; a gate oxide film on the channel portion of the base region; a gate electrode on the gate oxide film; a source electrode on source region; a drain electrode on the drain region; an interlayer film; a protection film; and a spiral polysilicon thin film on the field oxide film, one end of the thin film being connected to the drain electrode, another end of the thin film being connected to the source electrode, the thin film being formed of pn-diodes connected in series.

MIS semiconductor device with low on resistance and high breakdown voltage

Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region

A high voltage integrated circuit is provided which includes a first conductivity type semiconductor substrate, a first conductivity type isolation region that extends continuously from the first conductivity type semiconductor substrate, a substrate electrode formed on a surface of the first conductivity type isolation region, a second conductivity type island-like region that is formed on the first conductivity type semiconductor substrate, such that the entire periphery of the island-like region is surrounded by the first conductity type isolation region, and a plurality of high voltage MOSFETs that are connected to a common power source and operate independently of each other.

High voltage integrated circuit

A semiconductor device with a metal-insulator-semiconductor transistor and a limiter or sacrifice diode has predetermined breakdown voltage and constant withstand voltage. The device includes a special well region underlying a drain portion or contacting an edge of a drain portion.

Growing community of inventors

Nagano, Japan

Gen Tada