Megachips Corporation

Minolta Company, Ltd.

Minolta Camera Kabushiki Kaisha

Gen Sasaki

Hiroaki Kubo

Takashi Matsutani

Toru Ishii

Hiroshi Ootsuka

Tsutomu Honda

Nobuo Hashimoto

Yusuke Nara

Manabu Inoue

Hideki Nagata

Katsuyuki Nanba

Takehiro Katoh

Yusuke Mizuno

Kenji Mizumoto

Yoshihiko Azuma

Hirokazu Yagura

Keizou Ochi

Takeshi Ogoshi

Kenji Nakamura

Masahito Niikawa

Yasuhiro Morimoto

Yuki Haraguchi

Masahiro Moriyama

Hirokazu Naruto

Munehiro Mori

Hiroshi Kiten

Kazuma Takahashi

Kazuya Morimoto

Takeshi Aoi

Katsuya Hashimoto

An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps.

Image processing apparatus having a plurality of image processing blocks that are capable of real-time processing of an image signal

Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.

Image processing apparatus for processing image data to produce compressed image data and display data

Image processing apparatus having a buffer memory for image data storage

An image processing apparatus includes a first storage section and a second storage section, a storage control section, and a computation section. The storage control section sequentially acquires block images obtained as a result of dividing an input image, and stores the block image as a target block image in the first storage section, while storing, in the second storage section, image data of, in a region of the target block image, a region abutting un-inputted block images in the input image, as image data of an abuttal region. The computation section implements a resizing process for changing the size of the target block image by performing an interpolation calculation using image data of the target block image stored in the first storage section and the image data of the abuttal region stored in the second storage section.

Image resizing apparatus and method that interpolates image blocks with abuttal regions

An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5&#xd7;5 taps are connected in cascade in three stages, which enables low-pass filtering with 13&#xd7;13 taps.

An image processing unit includes a computing unit, a data input unit that inputs image data to the computing unit, a data output unit that outputs the image data computed by the computing unit, and a setting unit. The computing unit includes computing cells including multiple types of computing cells, input domain selectors, and at least one of output domain selectors. The setting unit sets the input domain selectors and the output domain selectors so that image data inputted by the data input unit to the computing unit on which desired computing has been performed by at least one computing cell among the computing cells is outputted from the data output unit.

Image processor including reconfigurable input and output domain selectors

An image processing apparatus includes: a relative coordinate acquisition part acquiring a corresponding position on an input image with respect to a predetermined pixel on an output image; a first storage part storing position information of the corresponding position; a reading control part causing pixel values of input pixels on the input image to be sequentially read; an organization part organizing a set of grid points formed of input pixels among input pixels read by the reading control part; a judgment part judging, based on the position information, whether or not pixel values of pixels in the vicinity of the corresponding position used in calculating a pixel value of the predetermined pixel have been read; a local memory storing, in a case where judgment is made that pixels in the vicinity of the corresponding position have been read, pixel values of pixels forming the set of grid points as pixel values of surrounding pixels regarding the predetermined pixel; and a pixel value calculation part calculating a pixel value of the predetermined pixel by interpolation using the pixel values of the surrounding pixels.

Image distortion processing apparatus, and method of operating an image distortion processing apparatus

The least significant bits of respective count values of an H counter and a V counter are combined, to generate a timing signal defining a 2&#xd7;2-size repeat block. A timing register including four registers each storing data which determines a color of each location within the repeat block is provided for each of input channels. A selector selects one of outputs of the timing registers based on the timing signal, and generates a signal designating a color of a pixel at a certain time for each of the input channels. A register storing black level correction data for each color is used in common by the input channels. For each of the input channels, an item of black level correction data at the certain time is selected based on the signal designating the color of the pixel at the certain time and input to a pre-processing circuit in each of the input channels.

Image processor for performing predetermined image processing in accordance with color selection timing signal

In a memory device, data can be transmitted from a first CPU to a second CPU via an individual register or a shared SRAM, for example. The data transmitted from the first CPU to the second CPU via the individual register also passes through a FIFO. When first data is transmitted via the shared SRAM and then second data is transmitted via the individual register, for example, and if the first data transmission is adjusted by a SRAM controller and put into a waiting state at the FIFO, the second data transmitted via the individual register also passes through the FIFO, preventing the second data transmission from being completed earlier than the first data transmission. The data transmissions can therefore be completed appropriately. This in turn increases reliability of the memory device.

Memory device that mediates mutual communication among a pluraliity of CPUs

Scanning image data and target image data are respectively stored in a first storage area and a second storage area. In one case, (J&#x2212;M+1)&#xd7;(K&#x2212;N+1)&#xd7;M&#xd7;N pieces of pixel data are stored as comparison image data relating to all comparison areas, and M&#xd7;N pieces of pixel data are stored as target image data. In contrast, the present invention requires the storage only of J&#xd7;K pieces of pixel data as scanning image data, and M&#xd7;N pieces of pixel data as target image data. This means the number of pieces of pixel data to be stored is reduced. In the case discussed above, one piece of target image data and (J&#x2212;M+1)&#xd7;(K&#x2212;N+1) pieces of pixel data relating to all comparison areas and corresponding to this target image data are stored. As compared to this case, the number of times pixel data are retrieved is reduced to 1/(M&#xd7;N), thereby shortening processing speed.

Block matching circuit and data update method

OSD data YD includes a color designating signal As and a color changing signal Ex. When a color register number is designated by the color designating signal As, a color storage unitoutputs an appropriate color signal. A Y signal is branched from the outputted color signal and subjected to a modulating process by the color changing signal Ex. The Y changing signal obtained by the modulating process is merged with a Cb signal and a Cr signal so as to form new color signal. The OSD data YD with changed color is subjected to a synthesizing process with image data XD according to the predetermined mixture ratio.

Color signal generating circuit, method and color signal synthesizing circuit

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Osaka, Japan

Gen Sasaki