Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Keyence Corporation

Gen Fukatsu

Genichiro Matsuda

Akimitsu Shimamura

Tetsuya Miyasaka

Ryota Nishikawa

The present invention aims to efficiently perform analysis from enormous data by utilizing information other than a device and a variable held by a basic unit. In addition, another object thereof is to extract and report important data from an analysis result of the enormous data. An analysis apparatus includes: a storage section that stores PLC information different from a symbol value among pieces of information associated with a programmable logic controller; an execution engine that repeatedly executes a user program; an acquisition section that acquires operation record data including a plurality of time-series symbol values, the operation record data being collected by execution of the user program; and a processing section that outputs an analysis report obtained by analyzing an abnormal symbol that does not satisfy a normal condition regarding the acquired operation record data based on the PLC information stored in the storage section.

Analysis apparatus, control method thereof, and analysis system

The method of controlling an information processing device according to the present invention is a method of controlling an information processing device which includes a processor having a cache memory, and a clock supplying unit that supplies a clock signal to the processor. The method includes: predicting a hit rate of the cache memory; and controlling the clock supplying unit so as to change a frequency of the clock signal in accordance with the predicted hit rate.

Method of controlling information processing device, information processing device, program, and program converting method

A design method for a semiconductor integrated circuit device wherein for a path having a signal arrival time longer than a desired signal arrival time, and among multiple paths in the semiconductor integrated circuit device, a path isolation is performed so that a number of other components to be connected to the output of a component belonging to the path decreases. The design method can be integrated into an automatic design flow using a legacy electronic design automation tool.

Design method for semiconductor integrated circuit device using path isolation

A semiconductor apparatus comprises a processor having an instruction register inside thereof, a pseudorandom number generating device activated in response to a test operation and generating pseudorandom numbers, an input switchover device for switching over between data input in normal operation and input of the pseudorandom numbers from the pseudorandom number generating device in the test operation to thereby output the data or pseudorandom numbers to the instruction register. The pseudorandom numbers generated in the pseudorandom number generating device are inputted to the instruction register via the input switchover device so that the random instructions are implemented and a random test is implemented with an activation rate equivalent to the same in the normal operation.

Semiconductor apparatus

In a testing method for a semiconductor memory using a memory BIST process, when it is difficult to carry out a comparing process in one cycle, a pipelining process is used for an expected value comparison, and in this case, in order to cut the number of flip-flops and to reduce an occupied area, at the time of a memory BIST process, a pipeline-use flip-flop and a scan-observing-use flip-flop and/or a scan-control-use flip-flop are used.

Growing community of inventors

Osaka, Japan

Gen Fukatsu