Maxim Integrated Products, Inc.

Geir Ostrem

John Frank Scampini

Yang Qian

Ed Liu

Yi Zhang

Brian Paul Brandt

Paul W Kalthoff

Ajay Kuckreja

Phillip Elliott

Philip Elliott

A continuous time delta sigma modulator includes a quantizer, a buffer module, and a reference module. The quantizer includes a comparator that updates a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module receives the digital output, stores the digital output for a predetermined delay period, and outputs the digital output after the predetermined delay period as a delayed digital output. The predetermined delay period is less than one cycle of the clock signal. The reference module selectively varies the reference potential based on the delayed digital output.

Digital technique for excess loop delay compensation in a continuous-time delta sigma modulator

A continuous time delta sigma modulator includes a quantizer and a reference module. The quantizer includes: a first comparator that generates a first digital output based on a comparison of a first reference potential with an input generated based on a sample of an analog signal; and a second comparator that generates a second digital output based on a comparison of a second reference potential with the input generated based on the sample of the analog signal. The reference module varies the first and second reference potentials based on the first and second digital outputs.

A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.

High speed digital to analog converter with reduced spurious outputs

Wide band CMOS digital to analog converters (DACs), including converters with selectable impulse response, using multiple DAC cores. The DAC cores operate on the same data at the DAC clock rate, but staggered in phase. Switches are used to switch the later part of the output time of each DAC core to the DAC output, otherwise to a dummy load. Thus each DAC conversion is comprised of a later part of each DAC core conversion, at least the first part of each DAC core conversion being ignored to allow each DAC core to settle before utilizing its output. Since the same switches and switching sequence is used on each DAC data conversion, the effects of switch imbalances are negated. Various embodiments are disclosed, including manipulation of the input to one of the DAC cores to selectively provide an NRZ, RZ and an RF response.

Wide band digital to analog converters and methods, including converters with selectable impulse response

Low distortion current switches for high speed current steering digital-to-analog converters. The current switches use a compensation method for improving the spurious peformance of a CMOS current steering DAC for high output frequencies caused by the capacitance of the common node of the switch transistors. For this purpose, a replica switch is provided, with the voltage change on the common node of the replica switch being used to provide a corresponding charge to the common node of the main switch in an amount equal to the charge needed to change the voltage on the common node of the main switch by the same amount as the voltage change on the common node of the replica switch. Multiple embodiments are disclosed.

Low distortion current switches for high speed current steering digital-to-analog converters

Current source arrays having a plurality of current sources arranged in an array of columns and rows are disclosed. The outputs of the current sources in even rows of the first column of an array are connected to the output of a current source in each of the other columns located along a first diagonal through the array from the respective current source in the first column. Also the outputs of the current sources in odd rows of the first column of the array are each connected to the output of a current source in each of the other columns located along a second diagonal through the array from the respective current source in the first column, the second diagonals being in an opposite diagonal direction from the first diagonals. When used in a current steering thermometer DAC, preferably but not necessarily, the current sources for the least significant bits are located on a main diagonal of the array.

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Colorado Springs, CO, United States of America

Geir Ostrem