Motorola Solutions, Inc.

Geetha B Nagaraj

Nicholas Giovanni Cafaro

Raul Salvi

Robert E Stengel

Joseph P Heck

Sumit Anil Talwalkar

Shafiullah Syed

Charles R Ruelke

Rodger W Caruthers

Ralf Hekmann

Christopher Calvo

Scott Miller

Thomas R Harrington

Nicholas G Cafaro

An improved superheterodyne receiver for a portable radio is provided. The receiver includes a frequency controller that applies pulse-shaped modulation to first and second LO signals in a synchronized manner. The frequency controller is steered by Artificial Intelligence (AI) based machine learning (ML) to determine first and second LOs that minimize image interference in the baseband signal.

Method and apparatus for mitigating image interference in a receiver

Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.

System and method for processing radiofrequency signals using modulation duty cycle scaling

Disclosed herein are systems for and methods of using a mirrored wideband baseband current for automatic gain control of an RF receiver. In an embodiment, a system includes an RF receiver having an adjustable gain and being configured to direct convert a received wideband RF signal to a wideband baseband current signal. The system further includes a current replicator coupled to the receiver and configured to generate a mirrored current of the wideband baseband current signal. The system further includes a wideband signal-level detector configured to receive the mirrored current from the current replicator, and to measure and output a signal-level value of the mirrored current. The system further includes an automatic gain-control circuit configured to receive the signal-level value from the wideband signal-level detector, and to adjust the gain of the receiver based at least in part on the received signal-level value.

Systems for and methods of using a mirrored wideband baseband current for automatic gain control of an RF receiver

A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.

Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer

A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Method and system for managing digital to time conversion

A method () of generating a composite mitigation signal () is presented. The composite mitigation signal includes an odd integer (N) of transitions () between a first amplitude and a second amplitude of the composite mitigation signal. Successive sets of the transition bursts are separated by a desired phase delay or time delay (), or such separations are defined by a base signal () having a frequency equal to a fundamental frequency of the composite mitigation signal. The composite signal generators () that generate the composite mitigation signal are also presented.

Generation of a composite mitigation signal with a desired spectral energy distrubution

A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An auto-tuning circuit and technique provide a measurement of static phase error by integrating the static phase error in the DLL/PLL circuit. A correction value is determined and applied as a current at the charge pump or as a time/phase offset at the phase detector to minimize static phase error. During normal operation the DLL/PLL is operated with the correction value resulting in substantially reduced spur levels and/or improved settling time.

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Coral Springs, FL, United States of America

Geetha B Nagaraj