Vanguard International Semiconductor Corporation

Geeng-Lih Lin

Ming-Dou Ker

Yeh-Ning Jou

Shao-Chang Huang

Shang-Hui Tu

Jui-Chun Chang

Kwang-Ming Lin

Karuna Nidhi

Federico Agustin Altolaguirre

Kun-Hsien Lin

Che-Hao Chuang

Yeh-Jen Huang

Shi-Hsiang Lu

Hung-Shern Tsai

Wen-Jya Liang

Hsin-Chyh Hsu

Chun-Chien Tsai

Shien-Wang Lo

Ming-Dou Der

A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.

Driving circuit

An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.

Integrated circuit and electrostatic discharge protection circuit thereof

An ESD protection circuit, which is coupled between either an I/O pad or a power pad and a ground terminal, includes a non-snapback device and a snapback device. When the voltage across the non-snapback device is not less than the non-snapback trigger voltage, the non-snapback device is turned on. When the voltage across the snapback device is not less than the snapback trigger voltage, the snapback device is turned on, and the voltage across the snapback device is held at the snapback holding voltage, in which the snapback holding voltage is less than the snapback trigger voltage. The non-snapback device and the snapback device are cascaded.

ESD protection circuits

A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.

Semiconductor device and method for manufacturing the same

An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively.

Electrostatic discharge protection device

The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

Semiconductor device and fabrication method thereof

A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current.

Cross-domain electrostatic discharge protection device

Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.

Semiconductor devices for high power application

A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.

Semiconductor device

An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

Electrostatic discharge protection circuits

ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Devices without current crowding effect at the finger's ends

An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is formed adjacent to the first side. The drain region which has a heavily doped region and a lightly doped region formed below the heavily doped region is formed adjacent to the second side. The width along a longitudinal axis of the heavily doped region has variable length and thus the length between one side of the heavily doped region to the second side has variable length.

A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

High voltage device with ESD protection

The present invention proposes an ESD protection circuit and its related circuits, suitable in an integrated circuit (IC), and coupled between a first pad and a second pad. When a power supply is provided to the IC, a bias generator generates a bias voltage to close the protection component. When the power supply is not provided to the IC, the protection component is always on to release the ESD stress between the first pad and the second pad.

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Jhudong, Taiwan

Geeng-Lih Lin