Anadigics, Inc.

Anadigies, Inc.

Gee Samuel Dow

Chun-Wen Paul Huang

Jianwen Bao

An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

CDMA power amplifier design for low and high power modes

A power amplifier circuit includes a power amplifier responsive to a power mode signal, the power amplifier having a power amplifier output node, and a power amplifier load circuit also responsive to the power mode signal, the power amplifier load circuit having a load circuit input node connected to the power amplifier output node. The power amplifier load circuit has a first transmission line coupled between the load circuit input node and a first node, a harmonic filter coupled between the load circuit input node and a common node, a first capacitor coupled between the first node and the common node, and a first switch coupled between the common node and ground, where the first switch is responsive to the power mode signal.

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Westlake Village, CA, United States of America

Gee Samuel Dow