Cirrus Logic Inc.

Micron Technology Incorporated

Geary L Leger

Peter R Carpenter

Karl H Mauritz

Bhoopal R Benjaram

Gary L Schaps

Thomas W Voshell

James M Shaffer

Joseph B Wicklund

John A Wishneusky

Sriraman Chari

Tong Tang

Steven H Laney

Chris A Unrein

Henry D Gerdes

John Andrew Wishneusky

James E Herrud

A computer system coupled to a network is disclosed which provides multiple paths for each serial input/output connection. In the receive mode, the current invention separates serial data frames which are composed of sub-functions/channels into sub-function data streams. The sub-function data streams can then be transferred out one at a time. In the transmit mode, the current invention forms data load patterns from the sub-function data streams. Each data load pattern is formed by selecting the appropriate binary bits from the sub-function data streams and arranging the binary bits selected in the sequence desired. The binary bits of each data load pattern are transmitted serially.

System for storing each of streams of data bits corresponding from a

A method and arrangement for shutting off a receive channel in a data communications system to prevent accidental or intentional overwhelming of the memory of the system such as that caused by a continuous burst of short frame data. The data frames received are monitored by a shutoff counter as they are received on one of the channels of a serial input/output (I/O) device. When the shutoff count is reached, the receive channel will be shut off. The current value of the shutoff counter is compared to a value stored in a warning register. Before reaching the shutoff count, a warning is generated when the current shutoff counter value reaches the warning register value.

Method and arrangement for shutting off a receive channel in a data

The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform. DC offset compensation of the encoded waveform is either removed prior to data decoding or after a data pre-decoding step; in either case the apparatus searches and detects predetermined substituted patterns in order to correct for the inversion or substitution. Further, a clock state generator is disclosed that uses precision silicon delays in order to generate clock states and quickly synchronize the states to the received encoded waveform. The clock states generate the recovered clocks required to decode data from the encoded waveform.

Bit rate doubler for serial data transmission or storage

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and multiple DMA controllers, on separate chips, coupled to the system interface bus. These multiple DMA controllers provide the system with multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel. The starting address of the free buffer is then determined and data is buffered within the free buffer.

DMA controller arrangement having plurality of DMA controllers and

This invention provides efficient and flexible data transfer management for a First-In First-Out (FIFO) buffer connects to a system bus and implements multiple data thresholds (e.g., two). Data transfer by the FIFO is controlled by either casually or more aggressively acquiring the system bus based on the amount of data inside the FIFO and on the state of the system bus. By balancing the bus activity level against the FIFO data level, bus access is facilitated at times when the bus has lower activity. This makes the FIFO less obtrusive when moving data across the bus. As a result, the bus is used more efficiently. The system bus is casually acquired when the FIFO data level reaches a soft threshold and the system bus is idle. Casual control of the system bus is relinquished when request from another device sharing the bus is received and a predetermined amount of data has been transferred. On the other hand, the system bus is more aggressively acquired when the FIFO data level reaches a hard threshold. Aggressive control of the system bus is relinquished only when data transfer is complete or when there is an emergency condition such as bus error. The thresholds can be dynamically adjusted based on the bus activity level. In another embodiment of the present invention, the amount of data transfer varies depending on whether the soft or hard threshold is crossed.

Apparatus for controlling FIFO buffer data transfer by monitoring bus

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel. The starting address of the free buffer is then determined and data is buffered within the free buffer.

DMA controller having multiple channels and buffer pool having plurality

An apparatus and method for efficiently receiving a long string of short data packets. Storing a long string of short data packets received from external devices can be inefficient in terms of system resources such as system memory and CPU time. In the preferred embodiment of the present invention, both the number of data packets in the FIFO buffer and the demand of system memory are monitored. A FIFO buffer of at least 32 bytes deep and having a packet-based threshold is implemented to monitor the number of data packets in the FIFO buffer. When the number of data packets in the FIFO buffer is equal to or exceeds the threshold and there is a predetermined number of free buffer memory available, data is transferred from the FIFO buffer to system memory. The number of data packets transferred from the FIFO buffer is also monitored to control the amount of data transfer. Any data stuck inside the FIFO buffer for a predetermined period of time is automatically unloaded. In an alternate embodiment, a FIFO buffer of at least 32 bytes deep and having an upper limit packet-based threshold and a lower limit packet-based threshold is used. A data transfer request is initiated when data in the FIFO buffer reaches the upper limit threshold. Conversely, a stop transfer request is initiated when data in the FIFO buffer is equal to or less than the lower limit threshold.

FIFO based receive packet throttle for receiving long strings of short

Apparatus for recovering data and clock information from an encoded

A circuit that controls, calibrates and monitors critical timing parameters in a computer system or network to prevent loss of, or inaccurate data, when transferring this data.

Timing calibrate and track control circuit

A fault-tolerant memory system or 'FTMS' is intended for use as mass data storage for a host computer system. The FTMS incorporates a dedicated microprocessor-controlled computer system which serializes blocks of user data as they are received from the host system, deserializes those blocks when they are returned to the host system, implements an error correction code system for the user data blocks, scrubs the data stored in the user memory, remaps data block storage locations within the user memory as initial storage locations therein acquire too may hard errors for error correction to be effected with the stored error correction data, and performs host computer interface operations. Data in the FTMS is not bit-addressable. Instead, serialization of the user data permits bytes to be stored sequentially within the user memory much as they would be stored on a hard disk, with bytes being aligned in the predominant direction of serial bit failure within the off-spec DRAM devices. Such a data storage method facilitates error correction capability.

Method and apparatus for storing digital data in off-specification

A printed circuit board is designed to conform to a single in-line memory module (SIMM) configuration, but includes multiple rows of the memory devices. By controlling a sequence of enable signals, selection of a single row from the multiple row of memory devices can be accomplished. The ability to address the different rows multiplies the memory capacity of the board by the number of rows of memory devices.

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Fremont, CA, United States of America

Geary L Leger