Intel Corporation

Pmc-Sierra, Inc.

Gavril Margittai

Zeev Sperber

Gabi Malka

Curtis Brian Lapadat

Mamta Bansal

Vikram Madhukar Labhe

Embodiments of the present invention relate to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle. Embodiment of the present invention may include a ring oscillator circuit. The ring oscillator includes an odd number of ordered inverting elements. One or more of the inverting elements may be an inverting memory element. Each inverting element's output port (except the last inverting element) may be operably connected to the subsequent inverting element's input port. The last inverting element's output port may be operably connected to the first inverting element's input port, thereby forming a chain or ring. A counter may be incremented by oscillations of an output port of an inverting element during a high portion of a periodic signal and may be decremented by oscillations of the output port of the inverting element during a low portion of the periodic signal. The end result in the counter may be proportional to the duty cycle offset of the periodic signal. The end value may then be used to correct the duty cycle of the periodic signal to a desired duty cycle offset.

Method and device for determining a duty cycle offset

An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

Texture engine memory access synchronizer

A single event upset (SEU) tolerant SRAM bit cell for six-transistor (6T), eight-transistor (8T), or multi-port RAM cell configurations fabricated in accordance with 0.18 &mgr;m or smaller CMOS processes. SEU tolerance is achieved without significantly increasing the cell's read and write cycle time and negligible impact on cell stability.

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Vancouver, Canada

Gavril Margittai