International Business Machines Corporation

Gavin Balfour Meil

Gabor Drasny

Jonathan James DeMent

Jason Nathaniel Dale

Adam P Burns

Jack DiLullo

Ronald P Hall

Ronald Nick Kalla

Steven Leonard Roberts

Benedikt Geukes

Christopher John Spandikow

Stephen J Barnfield

Jeffrey Mark Ritzinger

Kilaus-Dieter Schubert

Maya Safieddine

A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.

Automating addition of power supply rails, fences, and level translators to a modular circuit design

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition. Determining the output sequence includes determining whether signal transition representation(s) of the output sequence indicate an output gated clock waveform.

Clock-gating phase algebra for clock analysis

In some embodiments, a method for processing register transfer level code representing a circuit design can include: determining, by one or more processors based on the register transfer level code, a first group of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each of the group of signal transitions represents a nondeterministic transition from a first signal state to one or more other signal states; determining, at least one of the processors based on the register transfer level code, that a subgroup of signal transitions of the first group is glitch-free; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the glitch-free subgroup.

Circuit design analyzer

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence.

Phase algebra for virtual clock and mode extraction in hierarchical designs

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.

Conditional phase algebra for clock analysis

In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.

Glitch-aware phase algebra for clock analysis

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine a first sequence of signal transition representations of a first signal of a first module of a register level circuit design. The second module of the register level circuit design comprises the first module, arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of the first signal of the first module. The signal transition representations of a second signal are propagated from the second module to the first module using the first signal. The tool can determine whether a first mapping can be determined between the first sequence and the second sequence, where the second sequence is propagated through the first module.

Phase algebra for specifying clocks and modes in hierarchical designs

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in a register transfer level circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to one or more possible signal states. Determining the input sequence of signal transition representations includes determining that a subsequence of the input sequence of signal transition representations indicates at most one transition within the subsequence of the input sequence. The design tool can determine, based on the indicated component and on the determination that the subsequence indicates at most one transition, an output sequence of signal transition representations derived from the input sequence of signal transition representations.

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.

Phase algebra for analysis of hierarchical designs

Integrated circuits (ICs) rely on static timing analysis during their design to ensure that they will operate at desired frequencies. Delays between sequential elements (e.g., latches and flip-flops) are constrained to meet target clock periods. Certain signals, however, such as untimed nets may be excluded from timing constraints if the circuit function does not require these nets to switch and propagate to sequential elements within the clock period. However, a signal marked as 'untimed' may have been mistakenly specified by the designer as an untimed net. To verify that an untimed net does not negatively impact the function of the design logic, the embodiments herein generate upstream and downstream event networks using shadow logic that corresponds to design logic upstream and downstream of the untimed net. A metastability network coupled to these networks is used to model nondeterminism and metastability resulting from transitions or potential glitches on the untimed net.

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Round Rock, TX, United States of America

Gavin Balfour Meil