Other

Institute of Microelectronics

Gautham Viswanadam

Chee Chong Wong

A wafer level integration module and method for fabricating are disclosed according to a construction whereby semiconductor functional device fabrication is carried out only after interconnect structures are processed on a bare wafer. The fabrication and processing include forming interconnect structures in a first side of a wafer. An insulation layer is deposited on the first side of the wafer. A conductive layer is deposited on the insulation layer so as to fill the interconnect structures and contact the insulation layer on the walls thereof. The conductive layer on the interconnect structures forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The conductive layer including the interconnection contacts is exposed on the first side of the wafer. A semiconductor functional device is fabricated on the first side of the wafer and interconnected with the interconnection contacts during the fabricating. Portions of the first conductive layer associated with the interconnection vias are exposed from the second side of the wafer. A portion of the first conductive layer can be selectively removed to form interconnection via redistribution connection structures that can be filled with a low resistivity material to form low resistivity redistribution interconnect with the semiconductor functional device through the first conductive layer.

Wafer level integration module having controlled resistivity interconnects

A method and apparatus for manufacturing an integrated circuit (IC) device () is disclosed. A wafer () is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro-structures () that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface () of the wafer. The wafer with preformed conductive interconnect microstructures () are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side () devices are fabricated, the silicon material () is then removed from a second side () of the device wafer (), opposite the first side, to expose the high temperature conductive interconnect microstructures (). Contacts are formed on the second side of the device wafer using conductive metal. These contacts are electrically connected to the interior of the microstructures and thereby electrically connect with the functional device (). The dies (()),(()) are separated along the separation zones () between the dies to produce individualized functional and packaged dies, each of which serves as a fully packaged IC device ().

Wafer level integration module with interconnects

A method of manufacturing an integrated circuit (IC) device is disclosed. A wafer including multiple dies is processed to form solder bumps at the bond pad locations. A conductive substrate is patterned for routing traces and connection pads and partially etched. Routers are formed to electrically route a connection pad to the interior of its corresponding routing terminals. The etched connection pads corresponds to the plurality of bond pad locations of the IC chip. The bumped IC chip is aligned and attached to the conductive substrate through the connection pads and solder bumps. The attached IC chip and the first side of the conductive substrate are then encapsulated. Un-processed conductive material is then removed from a second side of the substrate, opposite the first side, to expose the routers and routing terminals. Contacts are formed on the second side of the substrate that electrically connect with the routers in the interior of the connection pads to thereby electrically connect with the connection terminals on the first side of the IC chip. The packaged IC are then separated along the separation lines to produce individualized dies. An IC device including a separated die is also disclosed.

Integrated circuit device and method of manufacturing thereof

A new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel and gold. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is printed into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away. The sacrificial layer is etched away to complete the formation of the solder bumps in the manufacture of the integrated circuit device. The etching away of the sacrificial layer insures the complete removal of all of the residue of the aperture mask.

Growing community of inventors

Singapore, Singapore

Gautham Viswanadam