Intel Corporation

Other

Gautham N Chinya

Hong Wang

Richard A Hankins

Bryant E Bigbee

Xiang Chris Zou

Baiju V Patel

John Thomas Shen

Prashant Sethi

Shivnandan D Kaushik

Per H Hammarlund

James Paul Held

John P Shen

Debabrata Mohapatra

Xinmin Tian

Anil Aggarwal

Sanjiv M Shah

John L Reid

Arnab Raha

Scott Dion Rodgers

Perry H Wang

Cormac Brick

Deepak A Mathaikutty

Jason W Brandt

Trung Am Diep

Ryan N Rakvic

Gad Shlomo Sheaffer

Dion Rodgers

Jamison D Collins

Robert P Knight

David K Poulsen

Hong Jiang

Quinn Able Jacobson

Chris J Newburn

Robert Geva

Huichu Liu

Arnab Paul

Ed Grochowski

Shiv Kaushik

Sang Kyun Kim

Asit K Mallick

Paul M Petersen

Yuval Yosef

Yoav Talgam

Shihao Ji

Chit Kwan Lin

Stephen J Tarsa

Kshitij Arun Doshi

Guei-Yuan Lueh

Edward Thomas Grochowski

Ali-Reza Adl-Tabatabai

Milind Baburao Girkar

Ittai Anati

Matthew C Merten

Ajay V Bhatt

Lance E Hacking

Ethan Schuchman

Suresh Srinivas

Aras Bilgen

Gustavo D Domingo Yaguez

Thomas J Hernandez

Murali M Annavaram

Thiam Wah Loh

Shirish Aundhe

Anne Weinberger Bracy

Marci Meingast

Stephen F Whalley

Anil Aggawal

Davi I Shaw

Reza Fortas

Ram K Krishnamurthy

Narayan Srinivasa

Bratin Saha

Koichi Yamada

Steven Hsu

Tsung-Han Lin

William A Stevens, Jr

Amit Agarwal

Douglas M Carmean

Gansha Wu

Helia A Naeimi

Julien Sebot

Jose Niell

Stephen J Robinson

Gokce Keskin

James Charles Abel

Bernard Lint

Josh Triplett

Shih-wei Liao

Khee Wooi Lee

Eric Kwesi Donkoh

Eckhard Delfs

Karthik Sankaranarayanan

Rangeen Basu Roy Chowdhury

Andreas Wasserbauer

Raymond Sung

Jim B Crossland

Rustam Miftakhutdinov

Swee Chong Peter Kuan

Marcus Z Comiter

Harnek Gulati

Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors

Systems, apparatuses and methods identify a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. The technology writes data to the first portion of the plurality of registers, and transfers the data from the first portion to the second portion.

Multi-buffered register files with shared access circuits

Methods and systems include a neural network system that includes a neural network accelerator. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.

Schedule-aware tensor distribution module

Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.

Methods and apparatus to load data within a machine learning accelerator

Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.

Performance scaling for dataflow deep neural network hardware accelerators

Systems, apparatuses and methods may provide for replacing floating point matrix multiplication operations with an approximation algorithm or computation in applications that involve sparse codes and neural networks. The system may replace floating point matrix multiplication operations in sparse code applications and neural network applications with an approximation computation that applies an equivalent number of addition and/or subtraction operations.

Multiplication-free approximation for neural networks and sparse coding

A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning

A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits

Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

Prefetcher for delinquent irregular loads

A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.

Migration of trusted security attributes to a security engine co-processor

Growing community of inventors

Hillsboro, OR, United States of America

Gautham N Chinya