Intel Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Idea Corporation

Gautam B Doshi

Roger A Golliver

Alan Hersh Karp

Jerome C Huck

Michael J Morrison

Glenn T Colon-Bonet

Peter Markstein

Sivakumar Makineni

Guillermo Juan Rozas

Kalyan Muthukumar

Sunnhyuk Kimn

John H Crawford

Gregory Scott Mathews

Stuart E Sailer

John Wai Cheong Fu

Robert S Norin

Bob Norin

Glen Colon-Bonet

Mike Morrison

A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.

Mechanism for software pipelining loop nests

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Methods and apparatus for controlling exponent range in floating-point calculations

A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is temporal, a replacement priority indicator associated with the identified cache entry is updated to reflect the access. When the targeted data is non temporal, the replacement priority indicator associated with the identified cache entry is preserved. The method may also be implemented by employing a first algorithm to update the replacement priority indicator for temporal data and a second, different algorithm to update the replacement priority indicator for non-temporal data.

Method and apparatus for managing temporal and non-temporal data in a single cache structure

A method and apparatus to handle exceptions. The method receives and prioritizes exceptions resulting from executing an instruction on different elements of an operand. The exceptions are reported to an interrupt service register which communicates the exceptions to an exception handler to effectively process the exceptions.

Exception reporting architecture for SIMD-FP instructions

Processor architecture having two or more floating-point status fields

The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to the parameterized prefetch instruction, and the address targeted by the prefetch instruction is adjusted. The registers are rotated for each loop iteration, and the prefetch instruction parameterized by the rotating register is adjusted accordingly. The number of iterations between prefetches for a given array is determined by the number of elements in the set of rotating register.

Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch

A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations

The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.

System and method for deferring exceptions generated during speculative execution

A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.

Scalar hardware for performing SIMD operations

A computer program product and method for multiplying a sparse matrix by a vector are disclosed. The computer program product includes a computer readable medium for storing instructions, which, when executed by a computer, cause the computer to efficiently multiply a sparse matrix by a vector, and produce a resulting vector. The computer is made to create a first array containing the non-zero elements of the sparse matrix, and a second array containing the end_of_row position of the last non-zero element in each row of the sparse matrix. A variable is initialized, and then, for each row of the second array, the computer is made to do one of two things. Either, it equates the variable to the sum of the variable and the product of a particular element of the first array and a particular element of the vector. Or, it equates a particular element of the resulting vector to the variable, and then equates the variable to a particular value.

Computer product and method for sparse matrices

Methods and apparatus for handling and storing bi-endian words in a floating-point processor

A method for software pipelining nested loops combines the inner and outer loops of the nested loop to form a merged loop. One or more operations from the outer loop are activated on selected passes through the merged loop, and the merged loop is software pipelined.

Method for software pipelining nested loops

A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Methods and apparatus for efficient control of floating-point status

An emulating agent and method is provided that receives numbers having si, exponents and significands of varying lengths and possibly configured in a variety of incompatible formats and to reformat the numbers into a standard uniform format for uniform arithmetic computations in processors operating with different architectures. In one embodiment, the emulating agent has a three-field superset register configured to receive the sign of a number in a first field, the exponent of a number in a second field and the significand of a number in a third field, regardless of the original format of the number, resulting in a number represented in a standard uniform format for computation. The embodiment also allows high level access to the fields to allow users to control the size of the numbers inserted into the fields.

Emulating agent and method for reformatting computer instructions into a

A saturating alignment shifter for use in the multiply and accumulate unit in a floating point arithmetic unit of a microprocessor that mimics the ideal model of an infinitely wide shifter. A saturation alignment shifter is provided that, in the case of the operation of A*B.+-.C, saturates at a predetermined shifting increment and, in the case where the mantissa of C is saturated, places the mantissa C in the left most significant bits. After adding C to A*B in a summation unit, the mantissa of A*B ends up in the right most significant bits and a single intervening bit, termed the bubble bit, remains between the mantissa of C and the mantissa of A*B. The bubble bit acts to mimic any intervening bits that would have occurred in the case of an ideal infinitely wide shifter. The new shifter eliminates hardware required for special cases and treats all operations with a single alignment shifter giving a system that is faster and more simple than conventional systems.

Growing community of inventors

Sunnyvale, CA, United States of America

Gautam B Doshi