Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Gautam Ashok Dusija

Chris Avila

Deepak Raghu

Yingda Dong

Man Lung Mui

Pao-Ling Koh

Jian Feng Chen

Chris Nga Yee Avila

Alexander Kwok-Tung Mak

Jianmin Huang

Mrinal Kochar

Seungpil Lee

Xiying Costa

Dana Lee

Abhijeet Manohar

Harish Reddy Singidi

Cynthia Hsu

Farookh Moogat

Jonathan Hsu

Daniel Edward Tuers

Changyuan Chen

Philip David Reusswig

Alex Mak

Piyush Girish Sagdeo

Yichao Huang

Chris Nga Yee Yip

Eran Sharon

Idan Alrod

Yehuda Hahn

Sergey Anatolievich Gorobets

Ramanathan Muthiah

Zhenming Zhou

Henry Chin

Zhenlei Shen

Ting Luo

Kulachet Tanpairoj

Daniel Joseph Linnen

Xinde Hu

Aaron Lee

Grishma Shah

Lei Chen

Venkatesh Ramachandra

Bo Lei

Anubhav Khandelwal

Sahil Sharma

Guirong Liang

Phil Reusswig

Evgeny Mekhanik

Lee M Gavens

Sourabh Sankule

Oleg Kragel

Abhilash Ravi Kashyap

Abhijit K Rao

Alexander K Mak

Matthew Davidson

Yi-Chieh Chen

Kalpit Bordia

Chris Yip

Dennis S Ea

Yew Yin Ng

Anne Pao-Ling Koh

Yiwei Song

Srinivasan Seetharaman

Tienchien Kuo

Vidhu Gupta

Chris Aviala

Neil Darragh

Alexander Kwog-Tung Mak

A storage system has a memory with a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block. The storage system repurposes the partially-bad SLC block as a non-volatile read cache for data stored in the MLC block (e.g., cold data that is read relatively frequently) to improve performance of host reads. Because the original version of the data is still stored in the MLC block, the original version of the data can be read if there is an error in the copy of the data stored in the partially-bad SLC block, thus avoiding the need for extensive error-correction handling to account for the poor reliability of the partially-bad SLC block.

Method and storage system with a non-volatile bad block read cache using partial blocks

A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

Data storage device with dynamic stripe length manager

Disclosed is an apparatus including a memory device. The memory device includes a memory array, a number of non-volatile memory sections configured to store a copy of operational information for the memory array, and a controller coupled to the number of non-volatile memory sections. The controller can responsive to a first wake-up operation, select a first non-volatile memory section as a starting section to retrieve the copy of operational information. The controller can responsive to a second wake-up operation, select a second non-volatile memory section as the starting section to retrieve the copy of operational information without regard to success of a prior attempt to retrieve the copy of operational information.

Systems and methods to wake up memory array

An error correction scheme in flash memory. Methods include extending a lifetime of a memory block, including: receiving an indication that an error occurred during a write operation at a first location in a memory block, the first location associated with a faulty page of the memory block; and performing a modified exclusive OR (XOR) scheme on the memory block by: performing a de-XOR operation that generates recovery data of the faulty page; storing the recovery data in a location different from the faulty page of memory; marking the faulty page for exclusion in future de-XOR operations; and performing a parity calculation that generates an updated parity value that includes all pages of the memory block that have been programmed except for the faulty page.

Error correction scheme in flash memory

The disclosure relates in some aspects to a read scrub design for a non-volatile memory that includes a block comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a trigger event associated with a read command performed on the first sub-block. A target sub-block test is then performed in response to a detection of the trigger event to determine whether to add the first sub-block to a read scrub queue. If the first sub-block is added to the read scrub queue, a sister sub-block test is then performed to determine whether to add the second sub-block to the read scrub queue.

Sub block mode read scrub design for non-volatile memory

In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell (MLC) block of the same memory die. A copy of source data from a respective SLC block is interleaved with a copy of source data from one or more other SLC blocks in the memory die to produce interleaved source data. Each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset. Each distinct set of the interleaved source data is written to a distinct respective MLC page of the MLC block.

On-chip copy with data folding in three-dimensional non-volatile memory array

The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.

Error detection for training non-volatile memories

A method for writing data to a NAND flash memory is disclosed, having steps of writing a first set of data to a first memory block, writing a second set of data to a second memory block, writing a third set of data to a third memory block and writing a fourth set of data to a XNOR memory block.

Methods and operations using XNOR functions with flash devices and solid state drives

Systems and methods for storing data in a multi-level cell (MLC) flash memory are disclosed. One such data storage system has a data path with cascaded data access performance, including multiple storage portions having different data access speeds. A cascaded data path enables flash memory data access that has a more graceful degradation instead of an abrupt decrease in performance during operation.

Multi-level cell solid state device and method for transferring data between a host and the multi-level cell solid state device

Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Techniques for reducing read disturb in partially written blocks of non-volatile memory

A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

Write redirect

Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.

Systems and methods for sampling data at a non-volatile memory system

Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

Proxy wordline stress for read disturb detection

Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks becomes defective. The first physical block of the first metablock may be replaced with the second physical block of the second metablock based on a determination that the health of the first physical block of the first metablock is different than the health of the second physical block of the second metablock.

Metalblock relinking to physical blocks of semiconductor memory in adaptive wear leveling based on health

Growing community of inventors

Milpitas, CA, United States of America

Gautam Ashok Dusija