International Business Machines Corporation

Freescale Semiconductor,inc.

Stmicroelectronics Gmbh

Globalfoundries Inc.

Tessera LLC

Gauri V Karve

Fee Li Lie

Sivananda K Kanakasabapathy

John Ryan Sporre

Eric R Miller

Bruce Bennett Doris

Hong He

Marc Adam Bergendahl

Kangguo Cheng

Sean Teehan

Stuart A Sieg

Lawrence Alfred Clevenger

Robert Russell Robison

Indira P Seshadri

Leigh Anne H Clevenger

Derrick Liu

Nicole A Saulnier

Mona Abdulkhaleg Ebrish

Juntao Li

Junli Wang

Ekmini Anuja De Silva

Srikanth Balaji Samavedam

Isabel Cristina Chu

Soon-Cheon Seo

Reinaldo Ariel Vega

Hosadurga K Shobha

Xuefeng Liu

Deepika Priyadarshini

Brent A Anderson

Terence B Hook

Andrew Mark Greene

Chun Wing Yeung

William James Taylor, Jr

Gen Tsutsui

Nicolas J Loubet

Qing Liu

Ruqiang Bao

Koji Watanabe

Mark Douglas Hall

Pietro Montanini

James Kenyon Schaeffer, Iii

Praveen Joseph

Gregory S Spencer

Daniel K Tekleab

Cristiano Capasso

Alexander Reznicek

Effendi Leobandung

Shogo Mochizuki

Dechao Guo

Balasubramanian Pranatharthiharan

Judson Robert Holt

Yann Mignot

Huiming Bu

Tara Lynn Astigarraga

Rajasekhar Venigalla

Muthumanickam Sankarapandian

Spyridon Skordas

Huimei Zhou

Scott David Halle

Ted R White

Timothy James McArdle

Sagarika Mukesh

Ravi K Bonam

Yue Ke

Russell Herbert Arndt

Gangadhara Raja Muthinti

Melissa Alyson Smith

Tien Ying Luo

Eric Raymond Evarts

Eric Miller

John M Grant

Eric C T Harley

Alex Richard Hubbard

Devika Sarkar Grant

Cody John Murray

Tien-Ying Luo

Shravan Kumar Matham

Debby Eades

A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Multilayer dielectric stack for damascene top-via integration

Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Physical unclonable function

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Structure and process to tuck fin tips self-aligned to gates

The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Secure fingerprinting of a trusted photomask

A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

Semiconductor device and method of forming the semiconductor device

A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

Elevator analytics facilitating passenger destination prediction and resource optimization

A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Substrate isolated VTFET devices

Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Sublithography gate cut physical unclonable function

A bilayer hardmask is formed on layers, the bilayer hardmask including a first hardmask layer and a second hardmask layer on the first hardmask layer. A first pattern is formed in the second hardmask layer, the first pattern including tapered sidewalls forming a first spacing in the second hardmask layer. A second pattern is formed in the first hardmask layer based on the first pattern, the second pattern comprising vertical sidewalls forming a second spacing in the first hardmask layer, the second spacing being reduced in size from the first spacing.

Bilayer hardmask for direct print lithography

A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.

Cognitive system for automatic risk assessment, solution identification, and action enablement

A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.

Embodiments of the invention are directed to a method that includes forming a fin over a major surface of a substrate. The fin includes an active fin region having a top fin surface and a fin sidewall. The top fin surface is substantially parallel with respect to the major surface, and the fin sidewall is substantially perpendicular with respect to the major surface. A gate is formed over and around a central portion of the fin, the gate having a bottom gate region and a top gate region. The bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall. The top gate region is substantially above the top fin surface and includes a top gate region sidewall that is at an angle with respect to the major surface.

Transistor gate having tapered segments positioned above the fin channel

A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

Structure and method for equal substrate to channel height between N and P fin-FETs

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Austin, TX, United States of America

Gauri V Karve