Lsi Logic Corporation

Gauri C Das

Ashok K Kapoor

Nicholas K Eib

Keith K Chao

Thomas G Mallon

Prabhakar Pati Tripathi

Ratan K Choudhury

Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.

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San Jose, CA, United States of America

Gauri C Das