Kla-tencor Technologies Corporation

Intermolecular, Inc.

Kla Tencor Corporation

Ultratech Stepper, Inc.

Other

Reel Solar, Inc.

Gaurav Verma

Kurt H Weiner

Tony P Chiang

Sandra Guy Malhotra

Imran Hashim

Prashant B Phatak

Somit Talwar

Rajesh Kelekar

Indranil De

Carl Hess

Bo Su

Karl-Josef Kramer

Rui-Fang Shi

Isabella Talley Lewis

Lance Glasser

Moshe E Preil

Scott A Andrews

Peter Nunan

William Volk

Ruifang Shi

Harold William Lehon

Hong Du

The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.

Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells

A pressure gauge may be coupled to a supply line which carries liquid from a bottle to either one or more mixing vessels and/or one or more reactors in a combinatorial processing tool. A control device may monitor the pressure measured by the pressure gauge, and the control device may be configured to change the pressure supplied to the bottle based on a comparison of the measured pressure to a predetermined pressure value. The control device may adjust the pressure provided to the bottle using a pressure regulator coupled to the pressure source. By changing the pressure provided to the bottle, the control device may maintain a relatively constant flow rate of fluids from the liquid source into one or more mixing vessels and/or the one or more reactors.

Maintaining flow rate of a fluid

In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Methods of combinatorial processing for screening multiple samples on a semiconductor substrate

A pressure gauge may be coupled to a vessel into which a liquid chemical is to be dispensed. The volume of the vessel may be known and a control device may determine an initial pressure of the vessel using the pressure gauge. A volume of liquid chemical may be dispensed into the vessel which may cause the pressure within the vessel to increase to a second pressure. The control device may determine the second pressure using the pressure gauge may calculate the volume of liquid chemical dispensed into the vessel using the volume of the vessel, the initial pressure of the vessel, and the second pressure of the vessel.

Measuring volume of a liquid dispensed into a vessel

Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs are provided. One method includes generating simulated images illustrating how each of the different reticle designs will be printed on a wafer at different values of one or more parameters of the wafer printing process. The method also includes detecting defects in each of the different reticle designs using the simulated images. In addition, the method includes determining a process window for the wafer printing process for each of the different reticle designs based on results of the detecting step.

Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs

A pressure gauge may be coupled to a supply line which carries liquid from a bottle to either one or more mixing vessels and/or one or more reactors in a combinatorial processing tool. A control device may monitor the pressure measured by the pressure gauge, and the control device may be configured to change the pressure supplied to the bottle based on a comparison of the measured pressure to a pre-determined pressure value. The control device may adjust the pressure provided to the bottle using a pressure regulator coupled to the pressure source. By changing the pressure provided to the bottle, the control device may maintain a relatively constant flow rate of fluids from the liquid source into one or more mixing vessels and/or the one or more reactors.

Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer are provided. One method includes generating simulated images of the reticle features printed on the wafer using different generated models for a set of different values of exposure conditions. The method also includes determining one or more characteristics of the reticle features of the simulated images. In addition, the method includes comparing the one or more characteristics of the reticle features of the simulated images to one or more characteristics of the reticle features printed on the wafer using a lithography process. The method further includes selecting one of the different generated models as the model to be used for predicting the printability of the reticle features based on results of the comparing step.

Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer

Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

Methods, systems, and carrier media for evaluating reticle layout data

Optical proximity correction methods and apparatus are disclosed. A simulated geometry representing one or more printed features from a reticle is generated using an optical proximity correction (OPC) model that takes into account a reticle design and one or more parameters from a process window of a stepper. An error function is formed that measures a deviation between the simulated geometry and a desired design of the one or more printed features. The error function takes into account parameters (p. . . p) from across the process window in addition to, or in lieu of, a best focus and a best exposure for the stepper. The reticle design is adjusted in a way that reduces the deviation as measured by the error function, thereby producing an adjusted reticle design.

Process window optical proximity correction

Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns similar to the test structure cells are also disclosed.

Apparatus and methods for detection of systematic defects

Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure. Far each localized defect, the same charged particle beam based tool may then be used to generate a high resolution image of the localized defect whereby the high resolution image can later be used to classify the each defect. In one embodiment, the defect's presence and location are determined without rotating the test structure relative to the charged particle beam.

Methodologies for efficient inspection of test structures using electron beam scanning and step and repeat systems

An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed. Additionally, searching mechanisms for quickly locating defects within such a test structure, as well as other types of voltage contrast structures, during a voltage contrast inspection are also provided.

Growing community of inventors

Sunnyvale, CA, United States of America

Gaurav Verma