Netlogic Microsystems, Inc

Xilinx, Inc.

Ampere Computing LLC

Rmi Corporation

Cypress Semiconductor Corporation

Applied Micro Circuits Corporation

Raza Microelectronics, Inc.

Gaurav Singh

Brian Hang Wai Yang

Wei-Han Lien

Mizanur Mohammed Rahman

Kjeld Svendsen

Kai-Yeung (Sunny) Siu

Daniel Chen

Dave Hass

Srivatsan Srinivasan

Millind Mittal

Sagheer Ahmad

Ygal Arbel

Frederick R Gruner

Ricardo Ramirez

Hai Ngoc Nguyen

Kiran B Kattel

Wei-Hsiang Chen

Brian Hang Wal Yang

David T Hass

Elango Ganesan

Cathal G Phelan

Hans Van Antwerpen

Gaurav Garg

Craig Stephen Forrest

Govind V Malalur

Sridhar P Subramanian

Kaushik Kuila

Herve LeTourneur

Christopher M Eccles

Lintsung Wong

Samir C Vora

Ali Kani

An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.

Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip

Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Priority framework for a computing device

Systems and methods are provided that facilitate cache miss detection in an electronic device. The system contains a probabilistic filter coupled to the processing device. A probing component determines existence of an entry associated with a request. The probing component can communicate a miss token without the need to query a cache. Accordingly, power consumption can be reduced and electronic devices can be more efficient.

Cache miss detection filter

An example method and system process a SuperSpeed packet transferred at a SuperSpeed transfer rate and based on processing the SuperSpeed packet, generate a Universal Serial Bus (USB) 2.0 packet to be transferred at a USB 2.0 transfer rate, the USB 2.0 transfer rate being less than the SuperSpeed transfer rate.

Systems and methods for super speed packet transfer

A network-on-chip system, method, and computer program product are provided for transmitting messages utilizing a centralized on-chip shared memory switch. In operation, a message is sent from one of a plurality of agents connected on a messaging network. The message is received at a central shared memory switch, the central shared memory switch being in communication with each of the plurality of agents. Further, the message is transmitted from the central shared memory switch to a destination agent, the destination agent being one of the plurality of agents.

Network-on-chip system, method, and computer program product for transmitting messages utilizing a centralized on-chip shared memory switch

A packet duplication control system including an input port for receiving a packet and a plurality of output ports for outputting duplications of the packet is disclosed. The duplications can be suitable to support a Virtual Local Area Network (VLAN) system. The duplications can be controlled by descriptors arranged in a linked-list table. Also, the descriptors can have encoding formats, such as contiguous range encoding, non-contiguous range encoding, and discrete encoding. Further, the linked-list table can include at least one shared descriptor.

Encoding-based multicast packet duplication control suitable for VLAN systems

Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure

An apparatus and method to receive first service request signals and second service request signals from virtual signal queues, to map the virtual signal queues according to a first mapping, to arbitrate the first service request signals in accordance with the first mapping of the virtual signal queues, and to re-map the virtual signal queues according to a second mapping, different from the first mapping, to allow arbitrating of the second service request signals in accordance with the second mapping of the virtual signal queues.

Advanced telecommunications router and crossbar switch controller

An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.

Age matrix for queue entries dispatch order

A multi-protocol communication circuit, for example, a serializer-deserializer (SerDes) circuit for communicating between an internal logic circuit and an external link includes a select terminal configured to accept a select signal representing a plurality of mode select signal. A SerDes core is coupled to the select terminal and configured to transmit outbound data conforming with a first communication protocol in response to a first mode select signal and conforming with a second communication protocol in response to a second mode select signal. The SerDes core is also configured to receive inbound data respective to a first communication protocol in response to a first mode select signal and respective to a second communication protocol in response to a second mode select signal. Advantages of the invention include the ability to provide high bandwidth communications between integrated circuits that employ different SerDes protocols.

Multi-protocol communication circuit

A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.

Prefix matching structure and method for fast packet switching

A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.

System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths

Growing community of inventors

Los Altos, CA, United States of America

Gaurav Singh