International Business Machines Corporation

Gaurav Mittal

Sanjay Dubey

Dung Q Nguyen

David James Hathaway

Susan Elizabeth Eisen

Arun Joseph

Kenneth Lundy Ward

Deepak K Singh

Ricardo H Nigaglioni

Christopher M Mueller

Glenn Owen Kincaid

Nagashyamala R Dhanwada

William W Dungan

Vikas Agarwal

Tu-An T Nguyen

Saiful Islam

Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.

Methods for generating a contributor-based power abstract for a device

A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

Finish status reporting for a simultaneous multithreading processor using an instruction completion table

A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

Instruction completion table with ready-to-complete vector

A system and method that uses a text-based script file to capture a circuit design and allows a circuit designer to manipulate the script file. The circuit designer can add, delete, or move components using various tags and commands that are stored in the script file. When the design is complete, or ready to be tested, the script file is processed creating a layout representation file that is readable by a graphics-based circuit design tool.

System and method for text based placement engine for custom circuit design

An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.

Energy-saving circuit and method using charge equalization across complementary nodes

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Round Rock, TX, United States of America

Gaurav Mittal