Anokiwave, Inc.

Viasat, Inc.

U.S. Monolithics, L.l.c.

Gaurav Menon

Nitin Jain

Jonathan P Comeau

David W Corman

Robert J McMorrow

Vipul Jain

Robert Ian Gresham

Kristian N Madsen

Scott R Humphreys

Kartik Sridharan

Shamsun Nahar

Jun Li

Akhil Garlapati

Antonio Geremia

Wade C Allen

Kenneth V Buer

Ramanamurthy V Darapu

Noyan Kinayman

Deborah Sue Dendy

Charles E Woods

Andrew Michael Street

Fnu Rajanish

Eythan Familier

Shmuel Ravid

Scott K Mitchell

Angelos Alexanian

Kevin B Greene

Dean Muellenberg

Christopher Jones

Amir Esmali

Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Phased array control circuit for controlling directivity of a beam-formed signal

A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.

Time-to-digital converter using voltage as a representation of time offset

A method and/or apparatus for tuning a frequency synthesizer device toward a prescribed frequency may input a signal into the input of the frequency synthesizer to produce an output signal having an output frequency, select a first one of a set of the above noted prescribed coarse curves, and compare the magnitude of the difference between the prescribed frequency and the output frequency. Next, the method selects a second of the set of coarse curves as a function of the magnitude of the difference between the prescribed frequency and the output frequency. Preferably, the method selects the second of the set of coarse curves by selecting one or more of the coarse curves out of the sequential frequency order as a function of the magnitude of the difference between the prescribed frequency and the output frequency.

Method and apparatus for tuning a synthesizer

Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.

Time-to-digital converter and calibration

Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Phase-aligning multiple synthesizers

A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Phased array architecture with distributed temperature compensation and integrated up/down conversion

A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially&#x2014;sequentially with regard to other beam-forming integrated circuits.

Phased array with low-latency control interface

A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.

Method and apparatus for heat sinking high frequency IC with absorbing material

In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Phased array control circuit for controlling the effective shape of a beam-formed signal

In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Phased array control circuit

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San Marcos, CA, United States of America

Gaurav Menon