Applied Materials, Inc.

United Test and Assembly Center Limited

Gaurav Mehta

James S Papanu

Arvind Sundarrajan

Guan Huei See

Upendra V Ummethala

Michael C Kutney

Glen T Mori

Eng Sheng Peh

Hien Boon Tan

Prayudi Lianto

Anthony Yi Sheng Sun

Chuen Khiang Wang

Karthik Elumalai

Susanto Tanary

Cheng Sun

Mary Annie Cheong

Sai Abhinand

Dimantha Rajapaksa

Pin Gian Gan

Ramesh Chidambaram

Amulya Ligorio Athayde

Sik Hin Chi

Shih-Chao Hung

Ricardo Fujii Vinluan

Wei Hao Kew

Michael Sorensen

Muhammad Adli Danish Bin Abdullah

Sri Thirunavukarasu

Mark McTaggart Wylie

Onkara Korasiddaramaiah

Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.

Electrostatic chuck with reduced current leakage for hybrid laser scribing and plasma etch wafer singulation process

Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.

Methods and apparatus for backside via reveal processing

A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active surface being electrically connected to the substrate. In the package, a second semiconductor chip the non-active surface of the second semiconductor chip is attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween. The active surface of the second semiconductor chip is electrically connected to the substrate. An encapsulant material covers the first and second semiconductor chips and their associated electrical connections. The encapsulating material fills the at least one gap between the plurality of adhesive portions and thereby encapsulates the second semiconductor chip and its associated electrical connection.

Stacked die packages

Growing community of inventors

Singapore, Singapore

Gaurav Mehta