Samsung Display Co., Ltd.

Netlogic Microsystems, Inc

Xilinx, Inc.

Gaurav Malhotra

Amir Amirkhany

Jalil Kamali

Roubik Gregorian

Anup P Jose

Mohamed N Elzeftawi

Younghoon Song

Kyunglok Kim

Karen Hovakimyan

Shiva Moballegh

Kenneth Hu

A system and method for configuring a serial receiver. In some embodiments, the method, includes: setting a threshold of a data slicer to a first threshold value; receiving, by the data slicer, a first data value; and setting the threshold of the data slicer to a second threshold value, the second threshold value being equal to the first threshold value plus a first adjustment, the first adjustment having the same sign as the first data value minus the first threshold value.

System and method for configuring serial receiver

A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1≤M≤Z, determining an Errorusing the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the Error. The adjusting of the input voltage may include generating a modified voltage V, whereinand each of A and B is determined using Σsign(Error).

Multi-pixel collective adjustment for steady state tracking of parameters

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Systems and methods for symbol-spaced pattern-adaptable dual loop clock recovery for high speed serial links

A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

Clock pattern detection and correction

A system and method for setting one or more compensation coefficients for a transistor. In some embodiments, a method for setting a first compensation coefficient for a transistor includes: determining a plurality of measured transistor currents, each at a respective one of a plurality of transistor control voltages; setting the first compensation coefficient based on the measured transistor currents and the transistor control voltages; and adjusting a voltage applied to a gate of the transistor based on the first compensation coefficient, the voltage corresponding to a color value.

System and method for transistor parameter estimation

A method of compensating for change in pixel and a display device incorporating such method are presented. The method includes dividing pixels into groups including a previous group L&#x2212;1, a current group L and a next group L+1; determining A[L] and B[L] for each pixel in the current group L; for each pixel in the current group L, determining a first moving average A[L] and a second moving average B[L] as follows: wherein A[L&#x2212;1] is a first moving average of a pixel in the corresponding column in the previous group L&#x2212;1, B[L&#x2212;1] is a second moving average of a pixel in the corresponding column in the previous group L&#x2212;1, and K is a moving average window; and for the next group L+1, setting a first initial value A[L+1] and a second initial value A[L+1] of each pixel to A[L] and B[L].

Fast external pixel compensation in a display panel

A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.

Estimation of pixel compensation coefficients by adaptation

A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.

Correlated double sampling pixel sensing front end

A method for compensating for characteristics of a transistor. In some embodiments, the method includes: measuring an error value, the error value being a difference between: a target current and a current driven by the transistor when the transistor is controlled by a compensated control signal based on an input control signal; adding to a first compensation parameter a first adjustment; adding to a second compensation parameter a second adjustment; and applying to a gate of the transistor a voltage equal to the sum of: the second compensation parameter, and the product of: the first compensation parameter, and an uncompensated drive voltage.

System and method for error adaptation

A transceiver system includes: a touch screen panel; a transmitter to transmit an input signal to an input line of the touch screen panel; a receiver to receive an output signal from an output line of the touch screen panel to detect a touch event on the touchscreen panel; and a state machine to set transmission frequencies of the input signal within a wideband operating frequency of the touch screen panel, and to calibrate the receiver to filter the output signal at the transmission frequencies of the input signal.

System and method for a transceiver system for touch detection

A system and method for digital differential detection includes a capacitive sensor having a first node and a second node, a transmitter configured to transmit an input signal through the first node and the second node, and a receiver coupled to the first node and the second node. The receiver is configured to receive a first modified input signal from the first node and a second modified input signal from the second node. The receiver includes first and second analog-to-digital converters configured to convert the first modified input signal to a first digital signal and the second modified input signal to a second digital signal. The receiver also includes a first differencing circuit configured to calculate a first difference between the first digital signal and a second digital signal and a decision circuit configured to output a result according to the first difference.

Digital differential detection for touch sensors

An apparatus for providing timing recovery in high speed links includes: an error sampler receiving an input signal and sampling the input signal; a phase detector comprising an error slicer; and a voltage-controlled oscillator (VCO). The error slicer generates an error signal corresponding to the input signal with respect to a voltage threshold. The phase detector generates a bit data corresponding to the error signal. The VCO changes a frequency of an output signal based on the bit data and locks the frequency at a phase in which an average of a plurality of input signals is equal to the voltage threshold.

Baud rate clock and data recovery (CDR) for high speed links using a single 1-bit slicer

A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.

System and method for setting analog front end DC gain

A data communication system includes a transmitter, a channel, and a receiver includes a Clock and Data Recovery (CDR) phase detector that is configured to: calculate an overall pulse response of the data communication system; obtain a function value for each of a plurality of phases, the plurality of phases corresponding to a resolution per symbol; set a crossing phase to be a phase at which this value is minimum among the plurality of phase; and set the CDR locking phase to be the crossing phase plus a midpoint from among the plurality of phases.

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Cupertino, CA, United States of America

Gaurav Malhotra