Texas Instruments Corporation

Other

Gaurav Chandra

Baher S Haroun

Prakash Easwaran

Krishnaswamy Nagaraj

Preetam Charan Anand Tadeparthy

Hisashi Shichijo

Venkatesh Srinivasan

Vijaya Bhaskar Rentala

Anant Shankar Kamath

Sumantra Seth

Danielle Griffith

Sumeet Mathur

Jomy G Joy

In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Process and temperature insensitive flicker noise monitor circuit

Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

Methods and apparatus for error cancelation in calibrated current sources

In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.

Scheme for non-linearity correction of residue amplifiers in a pipelined analog-to-digital converter (ADC)

In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Resistor self-trim circuit for increased performance

In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.

Apparatus and method for improving performance of sigma-delta modulators having non-ideal components

A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

High order trans-impedance filter with a single operational amplifier

A receiver, implemented with low noise and low distortion, to process an input signal containing signals of interest and unwanted interference signal. In an embodiment, the receiver contains a mixer which generates an intermediate signal in the form of an electric current, and a filter which filters the unwanted interference signals from the intermediate signal. The intermediate signal is centered around a lower frequency compared to a carrier frequency of the input signal. Due to the current mode interface between the mixer and the filter circuit, low noise and low distortion may be attained.

Reducing noise and distortion in a receiver system

A low distortion filter circuit implementing variable gain amplification (VGA). An aspect of the present invention increases the degrees of freedom (number of components which can be independently programmed/changed to corresponding desired values) to achieve a desired combination of D.C. gain and filter characteristics (e.g., corner frequency, Q-factor, notch frequency, etc.). Such additional degrees of freedom are attained by including additional components in either on input block or a feedback block (implemented with reference to an operational amplifier), and by redesigning the other block using principles such as admittance concellation to remove the effects of such additional components. The blocks are designed such that a terminal of the programmable components is connected to a fixed/constant voltage (e.g., ground). Embodiments implementing bi-quad single amplifier with and without notch are disclosed.

Filter circuit providing low distortion and enhanced flexibility to obtain variable gain amplification

A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.

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Richardson, TX, United States of America

Gaurav Chandra