Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Gaurav Agrawal

Deependra Kumar Jain

Krishna Thakur

Ravi Kumar

Ramji Gupta

Ravichandar Reddy Geetla

Kaushlendra Trivedi

Luv Pandey

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.

Digital frequency synthesizer

A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.

Multiphase digital frequency synthesizer with fractional division

An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Circuitry and methods for fractional division of high-frequency clock signals

An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.

Initialization circuit of delay locked loop

A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency.

Delay-locked loop having initialization circuit

A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated. In a final state, the first output signal is in the second state, the first control switch is deactivated, the second output signal is in the first state, and the second control switch is activated. The controller changes the first and second control signals only after the first and second output signals reach the respective second and first states.

High-speed voltage level shifter circuit

A delay-locked loop (DLL) has a fractional phase frequency (PF) detector that reduces false locking and harmonic locking. The PF detector has a trunk, an upper branch, a lower branch, and a logic module. A delay line provides the PF detector a set of fractional phase-delayed clock signals that are used to prime and/or activate corresponding flip-flops of the trunk, upper branch, and lower branch in a sequence. The use of flip-flops in the lower branch activated by different fractional phase-delayed clock signals avoids false locking and harmonic locking over a wider range of initial delay magnitudes than conventional DLLs.

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Aligarh, India

Gaurav Agrawal