Arm Limited

Gaurang Prabhakar Narvekar

Rahul Mathur

Yew Keong Chong

Andy Wangkun Chen

Bikas Maiti

Martin Jay Kinkade

Sanjay Mangal

Rajesh Reddy Challa

Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.

Redundancy circuitry for memory application

Various implementations described herein refer to an integrated circuit having dummy wordline driver circuitry coupled to a dummy wordline and dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline. The integrated circuit may include dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry. The dummy wordline tracking circuitry may have one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source.

Circuitry for tracking bias voltage behavior

Growing community of inventors

Austin, TX, United States of America

Gaurang Prabhakar Narvekar