Intel Corporation

Gaudencio Hernandez Sosa

Kai Xiao

Beom-Taek Lee

Raul Enriquez Shibayama

Varvara Kollia

Carlos Alberto Lizalde Moreno

Se-Jung Moon

Chien-Ping Kao

Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.

High speed differential pinout arrangement including a power pin

A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.

Structural optimization of contact geometry for high performance connector

In one embodiment, a receiver includes: a data path having a first slicer to receive and sample an incoming analog signal and to determine a bit level for the incoming analog signal, the first slicer to provide a bit decision to a consuming logic; an analysis path having a second slicer to receive and sample the incoming analog signal and to determine a second bit level for the incoming analog signal; and a controller coupled to receive an output of the first slicer and an output of the second slicer to determine a bit error rate for the data path based on the first and second slicer outputs. Other embodiments are described and claimed.

Measuring bit error rate during runtime of a receiver circuit

Growing community of inventors

Guadalajara, Mexico

Gaudencio Hernandez Sosa