International Business Machines Corporation

Gary Yuh Tsao

Wen-Tzer Thomas Chen, Jr

Cuong T Nguyen

Howard Carl Tanner

Binh Thai Hoang

Steven Mark Thurber

Giles R Frazier

Gary Dale Carpenter

Spencer Shepler

Yat Hung Ng

Son Hung Lam

Frank Dea

Keith Andre Braithwaite

Earl James McDonald

A module type distinguishing apparatus and method for differentiating between modules based upon the presence or absence of a pulling resistor at a specified pin connection of the modules. A high impedance pulling resistance is connected to the line and is subject to sensing while a tri-state mode of operation is initiated in the module. The presence or absence of the pulling resistor in the module is detected and recorded in a register. Differentiation between module types is accomplished based upon the binary state of the data in the register. In a particularized implementation, industry standard L2 cache modules are distinguished as to tag bit size depending on the presence or absence of a pulling resistor as detected during tri-state operation of a tag output pin.

Connected module type distinguishing apparatus and method

A network adaptor for receiving and processing Asynchronous Transfer Mode cells within a computer network is disclosed. The network adaptor includes a raw cell buffer, a control table, several Direct Memory Access buffers, and a Direct Memory Access controller. The raw cell buffer is utilized for receiving Asynchronous Transfer Mode cells from the computer network. The control table includes a multiple of virtual circuit identifier entries. When a corresponding virtual circuit identifier of the Asynchronous Transfer Mode cell is found in one of the multiple of virtual circuit identifier entries within the control table, one of the several Direct Memory Access buffers is set to receive the Asynchronous Transfer Mode cell. The Direct Memory Access controller is then utilized for initiating a Direct Memory Access transfer of the Asynchronous Transfer Mode cell from one of the several Direct Memory Access buffers when a pre-set threshold for Asynchronous Transfer Mode cell transfer is reached, such that Asynchronous Transfer Mode cell processing performance may be optimized to a receiving computer system in which the network adaptor is installed.

Adaptor for receiving and processing asynchronous transfer mode cells

A power supply interface suitable to provide voltages of appropriate magnitude to a static random access memory (SRAM) device from a combination of independent sources including a main power supply, an auxiliary power supply, and a battery. The voltages from the interface are at levels consistent with the SRAM modes of operation. During limited voltage tolerance read and write access operations, main power supply voltage is provided through a low forward voltage drop switched metal oxide field effect transistor (MOSFET). Parasitic paths, potentially producible by the transistor and affecting the battery source of power, are eliminated through the use of a second, complementary MOSFET. The second MOSFET is directly responsive to a POWERGOOD signal from the main power supply, indicating both an 'on' state and an appropriate voltage level of the main power supply.

Power supply interface circuit providing nonvolatile storage with

A frame-address matching function of a network controller is enhanced. In a full power-on mode, the controller performs conventional functions. In the low-power mode, the controller includes frame-address and frame-data matching, as well as pre-determined and programmable autonomous response to network protocol. If a match occurs with respect to the frame destination address or frame data, the system associated with the controller is placed in a wake-up state. If the controller is programmed to perform pattern matching inside the frame data area, upon such match in the frame data area the controller will generate and transmit on the network a simple response packet automatically. Conversely, if a match is not detected, no action is taken. The frame-data patterns are programmable with the capability to mask out certain data fields as desired which are protocol dependent and are substantially protocol dependent.

Programmable power management system and method for network computer

A system and method for asynchronously managing the issuance of program I/O store instructions from a high speed central processor to a multiplicity of relatively lower speed I/O adapter devices. An interface between the central processor and the I/O adapter devices includes a program I/O store queue, a state machine, and a token pool related in count to the concurrent processing capabilities of I/O controllers. The interface queue includes information for uniquely identifying program I/O store instructions by adapter device destination and user application program to manage error recovery. As preferably implemented, the interface system and method also distinctly manages program I/O instructions requiring synchronous execution, such as program I/O load instructions.

System and method for asynchronously processing store instructions to

In a computer system having multiple devices on a bus, a method for a first device on the bus to designate its own identifier including the steps of the first device transmitting on the bus a request for a device with a desired identifier to respond, determining that no device on the bus responds to the request, and upon such determination, designating the desired identifier to identify the first device to at least one of the multiple devices on the bus. In addition, in a computer system having multiple devices on a bus, a first device including apparatus for transmitting on the bus a request for a device with a desired identifier to respond, apparatus for determining that no device on the bus responds to the request, and apparatus for, upon such determination, designating the desired identifier to identify at least one of the first device to the multiple devices on the bus.

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Austin, TX, United States of America

Gary Yuh Tsao