United Microelectronics Corp.

United Semiconductor Corp.

United Semiconductor Circuit Corp.

United Microelectronics Coporation

Gary Y Hong

Chen-Chiu Hsue

Hwi-Huang Chen

Joe Ko

Anchor Chen

Chen-Chung Hsu

Ming-Tzong Yang

Yau-Kae Sheu

Yen-Lin Ding

Ching-Hsiang Hsu

Chih-Hung Lin

Ruei-Ling Lin

Wenchi Ting

Claymens Lee

Kan-Yuan Lee

Heng-Sheng Huang

Chen-Hui Chung

Hong-Tsz Pan

Hsiu-Wen Huang

Cheng H Huang

Weiching Horng

Chen Chiu Hsue

Yau-Kae Shell

Jhy-Jyi Sze

Sun-Chieh Chien

Cheng-Han Huang

Jason Jyh-shyang Jenq

Chih-Jen Huang

Robin Lee

Kun-Luh Chen

Yue-Shiun Lee

H J Wu

Ming-Tzung Yang

J S Jenq

Js Jason Jenq

Peter Chang

Lawrence Y Lin

Chen-Chih Hsue

Shyh-Jye Lin

Heng-Seng Huang

Wen-Chi Ting

Min-Tzong Yang

Ancheor Chen

Huang-Chung Cheng

Huan-Ping Su

Han-Wen Liu

Patrick Wang

Yueh-Hsun Lee

Ying-Jen Lin

Shih-Chieh Lin

Yang-Hui Fang

A method for operating a non-volatile memory device, which is applicable to an n-channel non-volatile memory device, wherein a positive voltage is applied to the control gate, a negative voltage is applied to the drain region while the source region is floating. Furthermore, a negative voltage is applied to the substrate to program to the n-channel memory device by the channel Fowler-Nordheim tunneling effect. To erase the n-channel non-volatile memory device, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, and the source region is floating. Moreover, a positive voltage is applied to the substrate to erase the n-channel memory device using the channel Fowler-Nordheim tunneling effect.

Method for operating a non-volatile memory

A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.

Method for measuring an effective channel length of a MOSFET

A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

Method for forming a cantilever beam model micro-electromechanical system

A transfer FET of a DRAM cell is formed having protective dielectric layers on the top and sides of the gate electrode. A first dielectric layer, preferably silicon dioxide, is provided over the transfer FET and a self-aligned etching process is used to etch through the first dielectric layer and to open a contact via to expose one of the source/drain regions of the transfer FET. A thick layer of polysilicon is deposited over the access circuitry and in contact with the exposed source/drain region of the transfer FET. A second dielectric layer is deposited over the surface of the thick layer of polysilicon and patterned to define a sacrificial structure on the polysilicon layer and over the one source/drain region. A third dielectric layer is deposited over the sacrificial structure and is anisotropically etched back to form sidewall spacer structures on the surface of the polysilicon layer. The sacrificial structure is removed and the spacer structures are used as a mask for shaping the thick polysilicon layer into at least part of a bottom capacitor electrode. The spacers are removed and a layer of hemispherical grained polysilicon (HSG-Si) is deposited over the surface of the etched thick polysilicon layer and etched back to transfer the textured surface of the HSG-Si to the underlying conventional polysilicon. A bottom capacitor electrode mask is used to define the lateral extent of the bottom capacitor electrode. The first dielectric layer acts as an etch stop in this process. A capacitor dielectric and a top capacitor electrode are provided to complete the DRAM cell capacitor and further processing continues to complete the DRAM.

Process for forming DRAM cell

The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% compared with the real gate length form SEM. Furthermore, the calculating method of the present invention only uses simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which have become more and more important in the device.

Method for measuring effective gate channel length during C-V method

In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line. The memory cell can be also erased by channel Fowler-Nordheim tunneling, in which the electrons is withdrawn from the floating gate through the tunnel oxide and channel to the substrate. In addition, the vertical two-transistor memory cell can be also programmed by conventional methods such as hot electron injection and drain Fowler-Nordheim tunneling, and can be also erased by negative gate source erase or drain Fowler-Nordheim tunneling erase.

Vertical two-transistor flash memory

A method of forming a self-aligned silicide layer. A planarization process is performed to form a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.

Method for forming a self-aligned silicide layer

A flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

High density flash memory cell

A method of fabricating a flash memory is described. First, a shallow trench isolation structure is formed on the substrate, so that the surface of the shallow trench isolation structure is projected above the surface of the substrate. Then, a spacer is formed on the sidewall of the shallow trench isolation structure, which projects above the surface of the substrate. With the spacer serving as a mask, a gate oxide layer not covered by the spacer is etched to expose the substrate. By thermal oxidation, a self-aligned tunneling oxide layer is formed on the exposed substrate. The spacer is then removed. A floating gate is formed on the tunneling oxide layer. In addition, a dielectric layer and a control gate are formed on the floating gate in sequence, thus completing the flash memory structure.

Method of fabricating flash memory

A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.

Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel

A flash memory structure comprises a first polysilicon layer above a semiconductor substrate; a thin dielectric layer above the first polysilicon layer; and a second polysilicon layer across and above the dielectric layer and the substrate, wherein the second polysilicon layer has a linear shape when viewed from the top. The memory structure further comprises a drain region in the semiconductor substrate on one side of the second polysilicon layer; a trench isolation structure for insulating from neighboring devices; a buried metallic layer located inside a portion of the trench isolation structure close to the upper surface of the substrate; and a common source region located on the other side of the first polysilicon layer just opposite the drain region such that the common source region at least includes a source region and a buried metallic layer alternately linked together.

Flash memory structure and method of manufacture

A method of fabricating a conductive line structure. A first dielectric layer is formed on a substrate. A conductive layer is formed on the first dielectric layer. The conductive layer is patterned to form an opening in the conductive layer. The opening exposes a portion of the first dielectric layer. A conformal stop layer is formed over the substrate. The conformal stop layer is conformal to the conductive layer. An oxide layer is formed in the opening. The oxide layer does not completely fill the opening. A portion of a sidewall of the opening is exposed. A spacer is formed on the exposed sidewall of the opening. The oxide layer is removed. A second dielectric layer is formed over the substrate to fill the opening. A void is formed in the second dielectric layer in the opening.

Method of fabricating conductive line structure

A method for forming a self-aligned silicide (or called salicide) structure in IC fabrication is described. This method is characterized by the step of making the top surface of a polysilicon-based structure into a rugged surface, which allows the subsequently formed salicide structure over the rugged surface of the polysilicon-based structure to have an increased surface area and thus have a reduced sheet resistance when compared to the prior art. By this method, the first step is to prepare a semiconductor substrate, after which an oxide layer is formed over the substrate. Next, a polysilicon-based structure is formed over the oxide layer, and then the exposed surface of the polysilicon-based structure is reshaped into a rugged surface. Subsequently, a silicide layer is formed over the rugged surface of the polysilicon-based structure, which serves as the intended salicide structure.

Method of forming a self-aligned silicide structure in integrated circuit fabrication

A method for manufacturing a cylindrical capacitor on a substrate includes the steps of providing a semiconductor substrate having a first conductive layer thereon, and then forming an insulation layer over the first conductive layer. The insulation layer can be a silicon nitride layer. The insulation layer is patterned to leave a portion of the patterned insulation layer above the node contact region. Thereafter, spacers are formed on the sidewalls of the patterned insulation layer such that the spacers are formed from a material that differs from the insulation layer and the first conductive layer. Next, an etching operation is conducted using the patterned insulation layer and the spacers as a mask to remove a portion of the first conductive layer. After that, the patterned insulation layer is removed. Then, a second etching operation is carried out using the spacers as a mask so that some more material from the upper portion of the first conductive layer is removed. Ultimately, a cylindrical shape structure that serves as the lower electrode of a capacitor is formed. Finally, the spacers are removed, and then a dielectric layer and a second conductive layer are sequentially formed over the cylindrical lower electrode to complete the fabrication of a cylindrical capacitor.

Method for manufacturing a cylindrical capacitor

A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

Method for fabricating inter-metal dielectric layer

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Hsin-Chu, Taiwan

Gary Y Hong