Honeywell International Inc.

Gary Warnica

Thom Kreider

Jon Douglas Gilreath

Ronald E Strong

Paul D Kammann

Vince J Gavagan, Iv

Vince J Gavagan Iv

A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.

Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture

A method for using an access triggered architecture for a computer implemented application is provided. The method receives a set of data at a designated functional block associated with a system memory location; performs an operation at the designated functional block, using the set of data, to generate a result, wherein the operation is performed each time information is received at the designated functional block; and returns the generated result to the system memory location.

Methods and apparatus to use an access triggered computer architecture

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Gary Warnica